Pixel unit, array substrate and manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9443983-B2
Application number	US-201414422414-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	Dec 13, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A pixel unit comprising a thin film transistor, a pixel electrode and a common electrode is provided. The common electrode and the pixel electrode form a capacitor. The pixel electrode is integrated with a drain of the thin film transistor. An array substrate comprising the pixel unit, a manufacturing method of the array substrate and a display device comprising the array substrate are also provided. In the pixel unit provided by the present invention, since the pixel electrode is integrated with the drain of the thin film transistor, it is not required to provide connection vias, so the manufacturing cost of an array substrate comprising the pixel unit is reduced.

First claim

The invention claimed is:

1. A pixel unit, comprising a thin film transistor, a pixel electrode and a common electrode, wherein the common electrode and the pixel electrode forming a capacitor, and the pixel electrode is integrated with a drain of the thin film transistor,
wherein the pixel unit further comprises a buffer layer, and a first via and a second via penetrating through the buffer layer, wherein the buffer layer covers a source of the thin film transistor, the drain of the thin film transistor and the pixel electrode, the active layer of the thin film transistor is located above the buffer layer, the source of the thin film transistor is connected to the active layer of the thin film transistor through the first via, and the pixel electrode is connected to the active layer of the thin film transistor through the second via.

2. The pixel unit according to claim 1 , wherein a material of an active layer of the thin film transistor comprises low-temperature polycrystalline silicon.

3. The pixel unit according to claim 2 , wherein the pixel unit further comprises a gate insulating layer which covers the active layer, and a gate of the thin film transistor is formed on the gate insulating layer.

4. The pixel unit according to claim 3 , wherein the gate of the thin film transistor comprises a first gate and a second gate spaced apart.

5. The pixel unit according to claim 3 , wherein the pixel unit further comprises a planarization layer located above the gate, and the common electrode is arranged on the planarization layer.

6. The pixel unit according to claim 5 , wherein the first via comprises a first left via and a first right via, wherein the first left via is located above the source of the thin film transistor and penetrates through the buffer layer, the gate insulating layer and the planarization layer, while the first right via is located above the active layer of the thin film transistor and penetrates through the gate insulating layer and the planarization layer; and
the pixel unit further comprises a first electrode, wherein a material of the first electrode is the same as that of the common electrode, the first electrode comprises a first left electrode filled in the first left via, a first right electrode filled in the first right via and a first connection electrode for connecting the first left electrode to the first right electrode, and the first connection electrode is located above the planarization layer.

7. The pixel unit according to claim 5 , wherein the second via comprises a second left via and a second right via, wherein the second left via is located above the active layer of the thin film transistor and penetrates through the gate insulating layer and the planarization layer, while the second right via is located above the pixel electrode and penetrates through the buffer layer, the gate insulating layer and the planarization layer; and
the pixel unit further comprises a second electrode, the material of the second electrode is the same as that of the common electrode, the second electrode comprises a second left electrode filled in the second left via, a second right electrode filled in the second right via and a second connection electrode for connecting the second left electrode to the second right electrode, and the second connection electrode is located above the planarization layer.

8. A display device, comprising an array substrate, wherein the array substrate comprises gate lines and data lines, the gate lines and data lines on the array substrate are interlaced with each other to divide the array substrate into a plurality of pixel regions, each of the pixel regions is provided therein with a pixel unit, and wherein the pixel unit is the pixel unit according to claim 1 ; and, within each of the pixel regions, a source of the thin film transistor is electrically connected to the corresponding data line, while a gate thereof is electrically connected to the corresponding gate line.

9. A display device, comprising an array substrate, wherein the array substrate comprises gate lines and data lines, the gate lines and data lines on the array substrate are interlaced with each other to divide the array substrate into a plurality of pixel regions, each of the pixel regions is provided therein with a pixel unit, and wherein the pixel unit is the pixel unit according to claim 1 ; and, within each of the pixel regions, at least a portion of the data line forms the source of the thin film transistor, while at least a portion of the gate line forms the gate of the thin film transistor.

10. The display device according to claim 9 , wherein an active layer of the thin film transistor comprises a first active region and a second active region spaced apart, both the first active region and the second active region are located beneath the corresponding gate lines; and, the gate of the thin film transistor comprises a first gate and a second gate spaced apart, a portion of the gate line facing the first active region forms the first gate of the thin film transistor, and a portion of the gate line facing the second active region forms the second gate of the thin film transistor.

11. The pixel unit according to claim 8 , wherein a material of an active layer of the thin film transistor comprises low-temperature polycrystalline silicon.

12. The pixel unit according to claim 11 , wherein the pixel unit further comprises a gate insulating layer which covers the active layer, and a gate of the thin film transistor is formed on the gate insulating layer.

13. The pixel unit according to claim 12 , wherein the pixel unit further comprises a planarization layer located above the gate, and the common electrode is arranged on the planarization layer.

14. The pixel unit according to claim 13 , wherein the first via comprises a first left via and a first right via, wherein the first left via is located above the source of the thin film transistor and penetrates through the buffer layer, the gate insulating layer and the planarization layer, while the first right via is located above the active layer of the thin film transistor and penetrates through the gate insulating layer and the planarization layer; and
the pixel unit further comprises a first electrode, wherein a material of the first electrode is the same as that of the common electrode, the first electrode comprises a first left electrode filled in the first left via, a first right electrode filled in the first right via and a first connection electrode for connecting the first left electrode to the first right electrode, and the first connection electrode is located above the planarization layer.

15. The pixel unit according to claim 13 , wherein the second via comprises a second left via and a second right via, wherein the second left via is located above the active layer of the thin film transistor and penetrates through the gate insulating layer and the planarization layer, while the second right via is located above the pixel electrode and penetrates through the buffer layer, the gate insulating layer and the planarization layer; and
the pixel unit further comprises a second electrode, the material of the second electrode is the same as that of the common electrode, the second electrode comprises a second left electrode filled in the second left via, a second right electrode filled in the second right via and a second connection electrode for connecting the second left electrode to the second right electrode, and the second connection electrode is located above the planarization layer.

16. A manufacturing method of an array substrate, compri

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Sun Jian
• Lei Dong
• An Seongjun
• Ryu Bongyeol

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title