Fin structure of FinFet

Patent metadata

Field	Value
Publication number	US-9443964-B2
Application number	US-201514793412-A
Country	US
Kind code	B2
Filing date	Jul 7, 2015
Priority date	Dec 28, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
etching a substrate of a first semiconductor material to form a mesa of the first semiconductor material;
etching an opening in the mesa;
depositing a first insulating material on a top surface of the mesa and surfaces of the opening;
depositing a second insulating material on the first insulating material in the opening;
recessing the first insulating material between the mesa and the second insulating material to below an uppermost surface of the second insulating material;
recessing the mesa to below the uppermost surface of the second insulating material;
depositing a channel layer on the mesa, the first insulating material, and the second insulating material, the channel layer comprising a second semiconductor material; and
forming a gate on the channel layer above a second isolation material.

2. The method of claim 1 , wherein the first insulating material has a U-shaped cross section.

3. The method of claim 1 , wherein the first semiconductor material is silicon and the second semiconductor material is germanium.

4. The method of claim 1 , further comprising forming isolation regions along opposing sides of the mesa prior to etching the opening in the mesa.

5. The method of claim 1 , wherein the first insulating material is silicon nitride.

6. The method of claim 1 , wherein the second insulating material is selected from the group consisting of silicon oxide, fluoride-doped silicate glass and a low-k dielectric material.

7. The method of claim 1 , wherein the channel layer is deposited by epitaxial deposition.

8. A method of forming a semiconductor device, comprising:
etching a substrate of a first semiconductor material to form a mesa of the first semiconductor material;
etching a recess in a top surface of the mesa;
depositing a first insulating material along sidewalls of the recess;
depositing a second insulating material in the recess along sidewalls of the first insulating material;
etching the first insulating material to remove at least a portion of the first insulating material between the first semiconductor material and the second insulating material;
recessing the mesa below an upper surface of the second insulating material;
depositing a channel layer along sidewalls of the second insulating material, the channel layer comprising a second semiconductor material;
forming a gate dielectric layer over the channel layer; and
forming a gate over the gate dielectric layer.

9. The method of claim 8 , wherein the first insulating material extends along a bottom of the second insulating material.

10. The method of claim 8 , wherein the channel layer extends over an uppermost surface of the second insulating material.

11. The method of claim 8 , wherein the first semiconductor material is silicon and the second semiconductor material is germanium.

12. The method of claim 8 , further comprising forming isolation regions along opposing sidewalls of the mesa prior to etching the recess in the top surface of the mesa.

13. The method of claim 8 , wherein the first insulating material is silicon nitride.

14. The method of claim 8 , wherein the second insulating material is selected from the group consisting of silicon oxide, fluoride-doped silicate glass and a low-k dielectric material.

15. The method of claim 8 , wherein the channel layer is deposited by epitaxial deposition.

16. A method of forming a semiconductor device, comprising:
recessing a substrate to form a mesa between adjacent recesses, the substrate comprising a first semiconductor material;
forming a first recess in a top surface of the mesa;
forming a first insulating material along sidewalls of the first recess;
forming a second insulating material over the first insulating material, the second insulating material filling the first recess;
removing at least a portion of the first insulating material to form a second recess between the mesa and the second insulating material;
removing a top portion of the mesa such that at least a portion of the second insulating material extends above an upper surface of the mesa;
forming a channel layer on the second insulating material, the channel layer including a second semiconductor material;
forming a gate insulating layer over the channel layer; and
forming a gate on the gate insulating layer.

17. The method of claim 16 , wherein the channel layer extends over an upper surface of the mesa.

18. The method of claim 16 wherein the first semiconductor material is silicon and the second semiconductor material is germanium.

19. The method of claim 16 , wherein the first insulating material extends along a bottom of the first recess.

20. The method of claim 16 , wherein the channel layer is deposited by epitaxial deposition.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Gin-Chen
• Jiang Ching-Hong
• Chen Neng-Kuo
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title