Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

Patent metadata

Field	Value
Publication number	US-9443936-B2
Application number	US-201313870184-A
Country	US
Kind code	B2
Filing date	Apr 25, 2013
Priority date	Dec 31, 2008
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.

First claim

What is claimed is:

1. A transistor comprising:
a quantum well in a substrate, the quantum well comprising a channel layer between a top barrier layer and a bottom buffer layer the channel layer comprising a channel material, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material;
a first junction region adjacent to the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;
a different second junction region adjacent to the quantum well, the second junction region through the channel layer, and to the bottom buffer layer; and
a junction material in the first junction region and in the second junction region, wherein the junction material has a lattice spacing larger than a lattice spacing of the channel material.

2. A transistor comprising:
a quantum well in a substrate, the quantum well comprising a channel layer between a top barrier layer and a bottom buffer layer the channel layer comprising a channel material, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material;
a first junction region adjacent to the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;
a different second junction region adjacent to the quantum well, the second junction region through the channel layer, and to the bottom buffer layer; and
a junction material in the first junction region and in the second junction region, the junction material having a lattice spacing different than a lattice spacing of the channel material, wherein the junction material comprises an alloy material at an interface between the channel layer and a metal material, and wherein the alloy material comprises the channel material and the metal material.

3. The transistor of claim 2 , wherein the metal comprises Nickel (Ni); wherein the channel material comprises germanium (Ge); wherein the top barrier layer and the bottom buffer layer comprise silicon.

4. The transistor of claim 2 , wherein the channel material comprises Indium Gallium Arsenide (InGaAs); wherein the junction material comprises InGaAs material having a higher concentration of Indium than a concentration of Indium of the channel material; wherein the top barrier material comprises Indium Phosphide (InP); wherein the bottom buffer layer comprises Indium Aluminum Arsenide (InAlAs).

5. A transistor comprising:
a quantum well in a substrate, the quantum well comprising a channel layer between a top barrier layer and a bottom buffer layer the channel layer comprising a channel material, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material;
a first junction region adjacent to the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;
a different second junction region adjacent to the quantum well opposite the first junction region, the second junction region through the channel layer, and to the bottom buffer layer; and
a junction material in the first junction region and in the second junction region, wherein the junction material has a lattice spacing larger than a lattice spacing of the channel material.

6. A transistor comprising:
a quantum well in a substrate, the quantum well comprising a channel layer between a top barrier layer and a bottom buffer layer the channel layer comprising a channel material, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material;
a first junction region adjacent to the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;
a different second junction region adjacent to the quantum well opposite the first junction region, the second junction region through the channel layer, and to the bottom buffer layer; and
a junction material in the first junction region and in the second junction region, the junction material having a lattice spacing different than a lattice spacing of the channel material, wherein the junction material comprises an alloy material at an interface between the channel layer and a metal material, and wherein the alloy material comprises the channel material and the metal material.

7. The transistor of claim 6 , wherein the metal comprises Nickel (Ni); wherein the channel material comprises germanium (Ge); wherein the top barrier layer and the bottom buffer layer comprise silicon.

8. The transistor of claim 6 , wherein the channel material comprises Indium Gallium Arsenide (InGaAs); wherein the junction material comprises InGaAs material having a higher concentration of Indium than a concentration of Indium of the channel material; wherein the top barrier material comprises Indium Phosphide (InP); wherein the bottom buffer layer comprises Indium Aluminum Arsenide (InAlAs).

9. A transistor comprising:
a quantum well in a substrate, the quantum well comprising a channel layer disposed vertically between a top barrier layer and a bottom buffer layer, the channel layer comprising a channel material, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material;
a first junction region horizontally adjacent to a first side of the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;
a different second junction region horizontally adjacent to a second side of the quantum well opposite the first side, the second junction region through the channel layer, and to the bottom buffer layer; and
a junction material in the first junction region and in the second junction region, wherein the junction material has a lattice spacing larger than a lattice spacing of the channel material.

10. A transistor comprising:
a quantum well in a substrate, the quantum well comprising a channel layer disposed vertically between a top barrier layer and a bottom buffer layer, the channel layer comprising a channel material, wherein the top barrier layer and the bottom buffer layer each comprise a material having a lattice spacing different than a lattice spacing of the channel material;
a first junction region horizontally adjacent to a first side of the quantum well, the first junction region through the channel layer, and to the bottom buffer layer;
a different second junction region horizontally adjacent to a second side of the quantum well opposite the first side, the second junction region through the channel layer, and to the bottom buffer layer; and
a junction material in the first junction region and in the second junction region, the junction material having a lattice spacing different than a lattice spacing of the channel material, wherein the junction material comprises an alloy material at an interface between the channel layer and a metal material, and wherein the alloy material comprises the channel material and the metal material.

11. The transistor of claim 10 , wherein the metal comprises Nickel (Ni); wherein the channel material comprises germanium (Ge); wherein the top barrier layer and the bottom buffer layer comprise silicon.

Assignees

• Majhi Prashant
• Hudait Mantu K
• Kavalieros Jack T
• Pillarisetty Ravi
• Radosavljevic Marko
• Dewey Gilbert
• Rakshit Titash
• Tsai Willman
• Intel Corp

Inventors

• Majhi Prashant
• Hudait Mantu K
• Kavalieros Jack T
• Pillarisetty Ravi
• Radosavljevic Marko
• Dewey Gilbert
• Rakshit Titash
• Tsai Willman

Classifications

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/801

  FETs having heterojunction gate electrodes · CPC title