Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9443930-B2
Application number	US-201514834465-A
Country	US
Kind code	B2
Filing date	Aug 25, 2015
Priority date	Sep 19, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate comprising an active region defined by a first trench, the activey region having a first conductivity type;
a device isolation layer provided in the first trench to surround the active region;
a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer; and
a gate insulating layer between the active region and the gate electrode,
wherein the device isolation layer comprises a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of a first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

2. The device of claim 1 , wherein the different layer is a first metal oxide layer that has an area oxygen density higher than that of the first silicon oxide layer.

3. The device of claim 2 , wherein the first metal oxide layer contains at least one of Al, Ti, Zr, Hf, Ir, Ta, or Mg.

4. The device of claim 2 , wherein the device isolation layer further comprises a second silicon oxide layer on the first metal oxide layer, a silicon nitride layer on the second silicon oxide layer, and a third silicon oxide layer on the silicon nitride layer.

5. The device of claim 1 , wherein the different layer is a first metal oxide layer that is extended from a bottom surface of the first trench to a top surface of the active region.

6. The device of claim 5 , wherein the first metal oxide layer surrounds the active region.

7. The device of claim 1 , wherein the active region is provided to have a second trench extending to the device isolation layer, and part of the gate electrode is disposed in the second trench.

8. The device of claim 7 , wherein the gate insulating layer comprises a second silicon oxide layer and a second metal oxide layer on the second silicon oxide layer, and
the second metal oxide layer has an area oxygen density lower than that of the second silicon oxide layer.

9. The device of claim 8 , wherein the second metal oxide layer contains at least one of La, Lu, Y, or Gd.

10. The device of claim 8 , wherein the second metal oxide layer extends between the gate electrode and the device isolation layer.

11. The device of claim 8 , wherein the gate electrode comprises a metal nitride layer in contact with the second metal oxide layer, and the metal nitride layer comprises TiN or WN.

12. The device of claim 11 , wherein the gate electrode further comprises a W or TiAl layer provided on the metal nitride layer to fill a lower portion of the second trench.

13. The device of claim 7 , wherein the gate electrode comprises a first gate electrode and a second gate electrode crossing each active region,
the device further comprises:
a first doped region formed between the first and second gate electrodes and in a central portion of the active region, the first doped region having a second conductivity type; and
second doped regions formed in edge portions of the active region, the second doped regions having the second conductivity type and being spaced apart from each other with the first and second gate electrodes interposed therebetween.

14. The device of claim 13 , wherein the first doped region has a bottom surface lower than that of the second doped region.

15. The device of claim 1 , wherein the different layer is a negatively-charged layer that contains F or Cl.

16. A semiconductor device, comprising:
a semiconductor substrate comprising an active region defined by a trench, the active region having a first conductivity type;
a device isolation layer provided in the trench to surround the active region;
a gate electrode, extending in a direction crossing the active region, and formed on the active region and the device isolation layer; and
a gate insulating layer between the active region and the gate electrode, the gate insulating layer having electric dipoles,
wherein the device isolation layer comprises an interface layer including a first silicon oxide layer conformally formed on an inner surface of the trench and a different layer, selected from one of a first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

17. The semiconductor device of claim 16 , wherein the gate insulating layer comprises a second silicon oxide layer and a second metal oxide layer on the second silicon oxide layer, and
the first metal oxide layer has an area oxygen density lower than that of the first silicon oxide layer.

18. The semiconductor device of claim 17 , wherein the gate insulating layer includes a first sub-layer that reduces an effective work function of the gate electrode and lowers the threshold voltage of the active region, and the interface layer includes a second sub-layer that counteracts the threshold voltage reduction of the gate insulating layer.

19. The semiconductor device of claim 18 , wherein the first sub-layer is the second metal oxide layer, and the second sub-layer is the first metal oxide layer.

20. A semiconductor device, comprising:
a semiconductor substrate comprising an active region defined by a trench, the active region having a first conductivity type;
a device isolation layer provided in the trench to surround the active region;
a gate electrode, extending in a direction crossing the active region, and formed on the active region and the device isolation layer; and
a gate insulating layer between the active region and the gate electrode,
wherein the gate insulating layer comprises a first silicon oxide layer and a first metal oxide layer on the first silicon oxide layer, and
the first metal oxide layer has an area oxygen density lower than that of the first silicon oxide layer.

Assignees

• Kim Junsoo
• Lee Dongjin
• Woo Dongsoo
• Lee Jun-Bum
• Han Sang-Il
• Samsung Electronics Co Ltd

Inventors

• Kim Junsoo
• Lee Dongjin
• Woo Dongsoo
• Lee Jun-Bum
• Han Sang-Il

Classifications

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title