Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9443863-B2
Application number	US-201514819841-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	Mar 4, 2010
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of first gate patterns on a substrate;
a dielectric pattern on the first gate patterns; and
a second gate pattern on the dielectric pattern;
wherein the second gate pattern comprises a first conductive pattern including polysilicon doped with a first impurity of a first concentration, a second conductive pattern including polysilicon doped with the first impurity of a second concentration, and a third conductive pattern including metal silicide, the first through third conductive patterns stacked sequentially,
wherein the second concentration is different from the first concentration.

2. The semiconductor device of claim 1 , wherein the first impurity comprises carbon (C), the second concentration is less than the first concentration.

3. The semiconductor device of claim 1 , wherein the first impurity comprises boron (B), the second concentration is greater than the first concentration.

4. The semiconductor device of claim 1 , wherein the first impurity further comprises oxygen (O), nitrogen (N), germanium (Ge), arsenic (As), and/or fluorine (F).

5. The semiconductor device of claim 1 , wherein the third conductive pattern includes the first impurity of a third concentration.

6. The semiconductor device of claim 5 , wherein one of the first through third concentrations is greater than remaining ones of the first through third concentrations.

7. The semiconductor device of claim 6 , wherein the one of the first through third concentration is about ten times to about thirty times greater than the remaining ones of the first through third concentrations.

8. The semiconductor device of claim 1 , wherein the third conductive pattern comprises cobalt silicide (CuSix), nickel silicide (NiSix), molybdenum silicide (MoSix), titanium silicide (TiSix), and/or tantalum silicide (TaSix).

9. The semiconductor device of claim 1 , further comprising:
a gate insulating layer between the plurality of first gate patterns and the substrate.

10. The semiconductor device of claim 1 , wherein the second gate pattern is extended along a direction on the plurality of first gate patterns.

11. The semiconductor device of claim 1 , wherein the gate layer is disposed in a peripheral region of the substrate.

Assignees

• Kim Jeeyong
• Lee Woonkyung
• Kim Sunggil
• Kang Jin-Kyu
• Lee Jung-Hwan
• Koo Bonyoung
• Hwang Kihyun
• Ju Byoungsun
• Noh Jintae
• Samsung Electronics Co Ltd

Inventors

• Kim Jeeyong
• Lee Woonkyung
• Kim Sunggil
• Kang Jin-Kyu
• Lee Jung-Hwan
• Koo Bonyoung
• Hwang Kihyun
• Ju Byoungsun
• Noh Jintae

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/032

  of conductive barrier, adhesion or liner layers · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D30/69 Primary

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title