Semiconductor device

Patent metadata

Field	Value
Publication number	US-9443816-B2
Application number	US-201514717757-A
Country	US
Kind code	B2
Filing date	May 20, 2015
Priority date	May 21, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A semiconductor device includes a semiconductor element, a substrate, a lead, and a sealing resin member. The semiconductor element has a first electrode and a second electrode located on opposite sides in the thickness direction. The substrate has an insulating base and a conductive plate. The base has first and second surfaces located on opposite sides in the thickness direction. The conductive plate is bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element. The lead has an island electrically connected to the first electrode. The sealing resin member covers at least the semiconductor element.

First claim

The invention claimed is:

1. A semiconductor device comprising:
at least one semiconductor element including a first electrode and a second electrode that are opposite to each other in a thickness direction;
a substrate including an insulating base and a conductive plate, the insulating base including a first surface and a second surface that are opposite to each other in the thickness direction, the conductive plate being bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element;
a lead including an island electrically connected to the first electrode; and
a sealing resin member covering the semiconductor element,
wherein the first electrode covers the entirety of one surface of the semiconductor element.

2. The semiconductor device according to claim 1 , wherein the base is made of ceramic.

3. The semiconductor device according to claim 2 , wherein the base is made of alumina.

4. The semiconductor device according to claim 1 , wherein the conductive plate is made of metal.

5. The semiconductor device according to claim 4 , wherein the conductive plate is made of Cu.

6. The semiconductor device according to claim 1 , wherein the conductive plate is not smaller in thickness than the base.

7. The semiconductor device according to claim 1 , further comprising a heat dissipation plate bonded to the second surface of the base.

8. The semiconductor device according to claim 7 , wherein the heat dissipation plate has an exposed surface exposed from the sealing resin member.

9. The semiconductor device according to claim 8 , wherein the exposed surface is flush with one surface of the sealing resin member.

10. The semiconductor device according to claim 7 , wherein the heat dissipation plate is made of metal.

11. The semiconductor device according to claim 10 , wherein the heat dissipation plate is made of Cu.

12. The semiconductor device according to claim 7 , wherein the heat dissipation plate is not smaller in thickness than the base.

13. The semiconductor device according to claim 1 , wherein the at least one semiconductor element is a plurality of semiconductor elements, and the island of the lead is electrically connected to the first electrodes of the plurality of semiconductor elements.

14. The semiconductor device according to claim 1 , wherein the lead includes a conductive portion electrically connected to the conductive plate of the substrate.

15. The semiconductor device according to claim 1 , wherein the island is formed with a plurality of recesses.

16. The semiconductor device according to claim 15 , wherein the island has a smooth part that coincides with the semiconductor element.

17. The semiconductor device according to claim 15 , wherein each of the recesses is circular in section.

18. The semiconductor device according to claim 15 , wherein the plurality of recesses are arranged to surround the semiconductor element.

19. The semiconductor device according to claim 1 , wherein the semiconductor element is a power semiconductor element through which an operating current flows.

20. The semiconductor device according to claim 19 , further comprising a bonding material that bonds the first electrode and the island.

21. The semiconductor device according to claim 20 , wherein the island is formed with a groove located outside the semiconductor element.

22. The semiconductor device according to claim 21 , wherein the bonding material lies inside the groove.

23. The semiconductor device according to claim 22 , wherein the groove surrounds the semiconductor element as a whole.

24. The semiconductor device according to claim 23 , wherein the island is formed with a plurality of recesses located outside the groove.

25. The semiconductor device according to claim 1 , wherein the lead includes a terminal that is connected to the island and exposed from the sealing resin member.

26. The semiconductor device according to claim 1 , wherein the substrate includes a terminal that protrudes from the sealing resin member.

27. A semiconductor device comprising:
at least one semiconductor element including a first electrode and a second electrode that are opposite to each other in a thickness direction;
a substrate including an insulating base and a conductive plate, the insulating base including a first surface and a second surface that are opposite to each other in the thickness direction, the conductive plate being bonded to the first surface of the base and electrically connected to the second electrode of the semiconductor element;
a lead including an island electrically connected to the first electrode; and
a sealing resin member covering the semiconductor element,
wherein the semiconductor element is a power semiconductor element through which an operating current flows,
the semiconductor device further comprises a drive IC through which a control current flows for controlling the operating current, and a first wire for connecting the drive IC to the conductive plate of the substrate, and
the conductive plate includes an extension that protrudes from the semiconductor element as viewed in plan and is connected to the drive IC via the first wire.

28. The semiconductor device according to claim 27 , wherein the extension is provided with a bonding chip to which the first wire is bonded.

29. The semiconductor device according to claim 28 , wherein the bonding chip includes a lower layer and an upper layer laminated to the lower layer, the lower layer being closer to the conductive plate than is the upper layer in the thickness direction.

30. The semiconductor device according to claim 29 , wherein the lower layer is made of Cu.

31. The semiconductor device according to claim 29 , wherein the upper layer is made of Ag.

32. The semiconductor device according to claim 28 , further comprising a second wire connected to the drive IC, wherein the second wire includes a first bonding portion, a step portion, a second bonding portion and a reinforced bonding portion, the second bonding portion having a shape that gradually decreases in thickness with increasing distance from the step portion, the reinforced bonding portion overlapping at least a part of the second bonding portion and exposing the step portion.

33. The semiconductor device according to claim 32 , wherein the reinforced bonding portion has a disk portion in contact with the second bonding portion.

34. The semiconductor device according to claim 33 , wherein the reinforced bonding portion has a column portion that is formed on the disk portion, is smaller in diameter than the disk portion, and is concentric with the disk portion.

35. The semiconductor device according to claim 34 , wherein the reinforced bonding portion includes a spire portion formed on the column portion.

36. The semiconductor device according to claim 32 , further comprising an annular mark formed by a capillary pressed in forming the second bonding portion.

37. The semiconductor device according to claim 36 , wherein the reinforced bonding portion exposes a part of the annular mark.

38. The semiconductor device according to claim 37 , wherein the reinforced bondin

Assignees

• Rohm Co Ltd

Inventors

• Koga Akihiro

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title