IC and IC manufacturing method

Patent metadata

Field	Value
Publication number	US-9443773-B2
Application number	US-201013148023-A
Country	US
Kind code	B2
Filing date	Jan 15, 2010
Priority date	Feb 6, 2009
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate ( 100 ) to form a buried region ( 150, 260 ) therein; forming a halo implant ( 134 ) using an impurity of a second type and a shallow implant ( 132 ) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region ( 150, 250 ); forming, adjacent to the halo implant ( 134 ), a further implant ( 136 ) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections ( 170, 160, 270 ) to the further implant ( 136 ), the shallow implant ( 132 ) and the buried region ( 150, 260 ) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.

First claim

The invention claimed is:

1. A method of manufacturing a vertical bipolar transistor in a CMOS process, comprising:
forming a collector by:
implanting an impurity of a first type into a substrate to form n-wells in the substrate and separated from one another at a predefined spacing; and
connecting, after implanting the n-wells, the n-wells by laterally diffusing the impurity of the first type from each of said n-wells into a portion of the substrate between the n-wells;
forming a halo implant using an impurity of a second type and a shallow implant using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over the laterally-diffused impurities of the collector, said halo implant vertically separating the shallow implant from the laterally-diffused impurities of the collector;
forming, laterally spaced from the halo implant, a further implant using an impurity of the second type for providing a conductive connection through a MOSFET channel and to the halo implant, wherein the MOSFET channel is formed in one of the n-wells; and
providing respective conductive connections to the further implant, the shallow implant and the collector allowing at least a portion of each of the shallow implant, the halo implant and the collector to be respectively operable as an emitter, base and collector of the vertical bipolar transistor.

2. The method of claim 1 , wherein the collector is formed with a pinched diffusion profile,
the emitter, base and collector of the vertical bipolar transistor are arranged vertically and in contact with one another, and
the collector of the vertical bipolar transistor includes the laterally-diffused impurity of the first type and is directly below the halo implant.

3. The method of claim 1 , wherein the collector is formed with a pinched diffusion profile between the n-wells and vertically below the halo implant and the shallow implant.

4. The method of claim 1 , further comprising:
forming a gate over said MOSFET channel;
providing a conductive connection to said gate; and
interconnecting the conductive connection to the gate and the conductive connection to the shallow implant.

5. The method of claim 1 , further comprising at least partially siliciding the shallow implant prior to providing said conductive connections.

6. The method of claim 5 , wherein said at least partially siliciding comprises depositing a siliciding metal over the shallow implant, patterning said siliciding metal and, after patterning said siliciding metal, at least partially siliciding the shallow implant according to said patterning.

7. The method of claim 1 , wherein forming the halo implant and forming the shallow implant include using a single mask.

8. The method of claim 1 , wherein the respective steps of forming the collector, forming the halo implant and forming the shallow implant include forming the collector, the halo implant and the shallow implant in a vertical stack with the halo implant being over and in contact with the collector and with the shallow implant being over and in contact with the halo implant.

9. An integrated circuit comprising:
a substrate;
a plurality of collector regions in the substrate;
n-wells in the substrate, each n-well having impurities of a first conductivity type;
a collector in each of the collector regions, each of the collectors extending laterally between and connecting a respective two n-wells of the n-wells to one another by laterally-diffused impurities from the respective two n-wells, the laterally-diffused impurities extending through an entire respective gap between the respective two n-wells and forming a pinched diffusion profile relative to the impurities of the respective two n-wells;
a plurality of halo implant regions comprising an impurity of a second conductivity type;
a plurality of shallow implant regions comprising the impurity of the first conductivity type; and
a further implant region comprising the impurity of the second conductivity type;
wherein a first set of some of the collector regions, halo implant regions and shallow implant regions form respective parts of respective CMOS transistors;
a second set of some of the plurality of collector regions, plurality of halo implant regions, further implant region, and plurality of shallow implant regions form respective parts of a vertical bipolar transistor in which one halo region vertically separates the laterally-diffused impurities of one collector region from one shallow implant region;
wherein the further implant region is located adjacent to the one halo implant region and configured and arranged to provide a conductive connection to the one halo implant region through a MOSFET channel, wherein the MOSFET channel is formed in one n-well of the respective two n-wells; and
wherein the vertical bipolar transistor further includes respective conductive connections to the second set of some of the shallow implant regions, the halo implant regions, and the collector regions for respectively operating as an emitter, base and collector of the vertical bipolar transistor.

10. The integrated circuit of claim 9 , wherein the pinched diffusion profile includes a diffusion profile that is thinner than an overall thickness of the respective two n-wells.

11. The integrated circuit of claim 9 , wherein said MOSFET channel being covered by a gate controlled by the conductive connection to the one shallow implant region.

12. The integrated circuit of claim 9 , wherein of the one shallow implant region of the vertical bipolar transistor is at least partially silicided.

13. An electronic device comprising: the integrated circuit of claim 9 , the integrated circuit being within a mobile communication device.

Assignees

• Vanhoucke Tony
• Heringa Anco
• Donkers Johannes Josephus Theodorus Martinus
• Slotboom Jan Willem
• Nxp Bv

Inventors

• Vanhoucke Tony
• Heringa Anco
• Donkers Johannes Josephus Theodorus Martinus
• Slotboom Jan Willem

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D62/137

  Collector regions of BJTs · CPC title

• H10D10/421

  having both emitter-base and base-collector junctions ending at the same surface of the body · CPC title

• H10D84/0109 Primary

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title