Method of forming metal contacts in the barrier layer of a group III-N HEMT

Patent metadata

Field	Value
Publication number	US-9443737-B2
Application number	US-201313856016-A
Country	US
Kind code	B2
Filing date	Apr 3, 2013
Priority date	Apr 3, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

First claim

What is claimed is:

1. A method of forming a high electron mobility transistor comprising:
etching a layered structure with a first gas combination to form a number of metal contact openings, the layered structure including a buffer layer that touches and lies over a substrate, a channel layer that touches and lies over the buffer layer, and a barrier layer that touches and lies over the channel layer, each of the metal contact openings having a first bottom surface that lies above and spaced apart from a top surface of the channel layer; and
etching the layered structure with a second gas combination to deepen the first bottom surface of each metal contact opening a distance to a second bottom surface that lies below the first bottom surface, the second bottom surface lying above and spaced apart from the top surface of the channel layer, wherein the second gas combination etches more of the barrier layer than does the first gas combination and wherein the first gas combination also etches through a cap layer that touches and lies above the barrier layer, and through a passivation layer that touches and lies above the cap layer, the cap layer including GaN, the passivation layer including silicon nitride.

2. The method of claim 1 and further comprising depositing a metal contact layer that touches each second bottom surface and fills up the metal contact openings.

3. The method of claim 2 and further comprising planarizing the metal contact layer to form a number of spaced-apart metal contacts that lie in the number of metal contact openings, and touch the barrier layer.

4. A method of forming a high electron mobility transistor comprising:
etching a layered structure with a first gas combination for a period of time to form a number of metal contact openings, the layered structure including a buffer layer that touches and lies over a substrate, a channel layer that touches and lies over the buffer layer, and a barrier layer that touches and lies over the channel layer, each of the metal contact openings having a first bottom surface that lies above and spaced apart from a top surface of the channel layer; and
etching the layered structure with a second gas combination to deepen the first bottom surface of each metal contact opening a distance to a second bottom surface that lies below the first bottom surface, the second bottom surface lying above and spaced apart from the top surface of the channel layer, wherein the period of time includes a first sub-period of time and a subsequent second sub-period of time and wherein the first gas combination etches the barrier layer to a depth for the first sub-period of time, and substantially no deeper after the first sub-period of time during the second sub-period of time, wherein the barrier layer is etched with the second gas combination for a predetermined period of time, wherein the first gas combination includes boron trichloride (BCl3) and sulfur hexafluoride (SF6), and wherein the second gas combination includes boron trichloride (BCl 3 ) and chlorine (Cl 2 ).

5. A method of forming a high electron mobility transistor comprising:
etching a GaN material of a barrier layer with a gas combination that includes boron trichloride (BCl 3 ) and sulfur hexafluoride (SF 6 ) to form a number of metal contact openings, the barrier layer being formed on a channel layer each of the metal contact openings having a bottom surface that lies above and spaced apart from a top surface of the channel layer; and
etching the GaN material of the barrier layer exposed by the metal contact openings with a gas combination that includes boron trichloride (BCl 3 ) and chlorine (Cl 2 ) to deepen each metal contact opening to a second bottom surface, the second bottom surface lying above and spaced apart from the top surface of the channel layer.

6. The method of claim 5 and further comprising depositing a metal contact layer that touches each second bottom surface and fills up the metal contact openings.

7. The method of claim 6 and further comprising planarizing the metal contact layer to form a number of spaced-apart metal contacts that lie in the number of metal contact openings, and touch the barrier layer.

8. The method of claim 5 wherein the gas combination that includes BCl 3 and Cl 2 etches more of the barrier layer than does the gas combination that includes BCl 3 and SF 6 .

9. The method of claim 5 wherein the gas combination that includes BCl 3 and SF 6 also etches through a cap layer that touches and lies above the barrier layer, and through a passivation layer that touches and lies above the cap layer.

10. The method of claim 9 wherein the cap layer includes GaN, and the passivation layer includes silicon nitride.

11. The method of claim 5 wherein the gas combination that includes BCl 3 and SF 6 also etches through a passivation layer that touches and lies above the barrier layer.

12. The method of claim 11 wherein the passivation layer includes silicon nitride.

13. The method of claim 5 wherein the channel layer includes GaN.

14. The method of claim 5 , wherein the GaN material of the barrier layer is AlGaN.

Assignees

• Texas Instruments Inc

Inventors

• Kondo Yoshikazu
• Wada Shoji
• Yamasaki Hiroshi
• Iwamoto Masahiro

Classifications

• H10P50/246

  of Group III-V materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title