Non-volatile memory device and method of programming the same

Patent metadata

Field	Value
Publication number	US-9443596-B2
Application number	US-201414192544-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Mar 15, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator generates a program voltage, a first pass voltage, and a second pass voltage. A first boost channel voltage applied when programming an outermost memory cell from among the memory cells of each of non-selected cell strings of the cell strings is lower than a second boost channel voltage applied when programming one of remaining memory cells except for the outermost memory cell. The non-volatile memory device prevents programming disturb caused by hot carrier injection.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a memory cell array having a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor; and
a voltage generator to generate a program voltage, a first pass voltage, and a second pass voltage,
wherein when programming one of the outermost memory cells of the plurality of memory cells a first boost channel voltage is generated based on the first pass voltage applied to word lines of ones of the memory cells other than the one of the outermost memory cells and when programming one of the memory cells of the plurality of memory cells other than the outermost memory cells of the plurality of memory cells a second boost channel voltage is generated based on the second pass voltage applied to word lines of ones of the memory cells other than the one of the memory cells of the plurality of memory cells being programmed;
wherein a level of the first boost channel voltage is lower than a level of the second boost channel voltage; and
wherein a level of the first pass voltage is lower than a level of the second pass voltage.

2. The non-volatile memory device of claim 1 , wherein the first boost channel voltage is formed by combining the program voltage applied to a word line of the one of the outermost memory cells with the first pass voltage applied to the word lines of the ones of the memory cells other than the one of the outermost memory cells,
the second boost channel voltage is formed by combining the program voltage applied to a word line of the one of the memory cells of the plurality of memory cells other than the outermost memory cells of the plurality of memory cells and the second pass voltage applied to the word lines of the ones of the memory cells other than the one of the memory cells of the plurality of memory cells.

3. The non-volatile memory device of claim 1 , wherein ones of the plurality of cell strings that are non-selected for programming are driven according to a self-boost scheme, or a local boost scheme.

4. The non-volatile memory device of claim 1 , wherein the first boost channel voltage is formed through a self-boost scheme and the second boost channel voltage is formed through a local boost scheme.

5. The non-volatile memory device of claim 1 , wherein a number of the word lines combined to form a first boost channel, which forms the first boost channel voltage, to receive the first pass voltage is larger than a number of the word lines combined to a form second boost channel, which forms the second boost channel voltage, to receive the second pass voltage.

6. The non-volatile memory device of claim 1 , wherein a condition to set the first boost channel voltage lower than the second boost channel voltage is that a number of programs is equal to or greater than a critical number causing programming disturb due to accumulated hot carrier injection into the one of the outermost memory cells.

7. The non-volatile memory device of claim 1 , wherein a first dummy memory cell is interposed between the ground select transistor and the memory cells, and a second dummy memory cell is interposed between the string select transistor and the memory cells.

8. A method of programming a non-volatile memory device including a memory cell array having a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor, and a voltage generator to generate a program voltage, a first pass voltage, and a second pass voltage, the method comprising:
generating a first boost channel voltage responsive to programming one of the outermost memory cells of the plurality of memory cells, the first boost channel voltage being generated based on the first pass voltage applied to word lines of ones of the memory cells other than the one of the outermost memory cells; and
generating a second boost channel voltage responsive to programming one of the memory cells of the plurality of memory cells other than the outermost memory cells of the plurality of memory cells, the second boost channel voltage being generated based on the second pass voltage applied to word lines of ones of the memory cells other than the one of the memory cells of the plurality of memory cells being programmed;
wherein a level of the first boost channel voltage is lower than a level of the second boost channel voltage; and
wherein a level of the first pass voltage is lower than a level of the second pass voltage.

9. The method of claim 8 , wherein the first boost channel voltage is formed by combining the program voltage applied to a word line of the one of the outermost memory cells with the first pass voltage applied to the word lines of the ones of the memory cells other than the one of the outermost memory cells,
the second boost channel voltage is formed by combining the program voltage applied to a word line of the one of the memory cells of the plurality of memory cells other than the outermost memory cells of the plurality of memory cells and the second pass voltage applied to the word lines of the ones of the memory cells other than the one of the memory cells of the plurality of memory cells.

10. The method of claim 8 , wherein ones of the plurality of cell strings that are non-selected for programming are driven according to a self-boost scheme, or a local boost scheme.

11. The method of claim 8 , wherein the first boost channel voltage is formed through a self-boost scheme, and the second boost channel voltage is formed through a local boost scheme.

12. The method of claim 8 , wherein a number of the word lines combined to form a first boost channel, which forms the first boost channel voltage, to receive the first pass voltage is larger than a number of the word lines combined to a form second boost channel, which forms the second boost channel voltage, to receive the second pass voltage.

13. The method of claim 12 , wherein a level of the first pass voltage is lower than a level of the second pass voltage.

14. The method of claim 8 , wherein a condition to set the first boost channel voltage lower than the second boost channel voltage is that a number of programs is equal to or greater than a critical number causing programming disturb due to accumulated hot carrier injection into the one of the outermost memory cells.

15. A non-volatile memory device, comprising:
a memory cell array having a plurality of cell strings in which a plurality of memory cells are connected with each other in series; and
a voltage generator to generate a program voltage, a first pass voltage, and a second pass voltage, to generate a first boost channel voltage responsive to programming one of the outermost memory cells of the plurality of memory cells, the first boost channel voltage being generated based on the first pass voltage applied to word lines of ones of the memory cells other than the one of the outermost memory cells, and to generate a second boost channel voltage responsive to programming one of the memory cells of the plurality of memory cells other than the outermost memory cells of the plurality of memory cells, the second boost channel voltage being generated based on the second pass voltage applied to word lines of ones of the memory cells other than the one of the memory cells of the plurality of memory cells being programmed;
wherein a level of the first boost channel voltage is lower than a level of the second boost channel voltage;
wherein a level of the first pass voltage

Assignees

• Lee Chang-Hyun
• Samsung Electronics Co Ltd

Inventors

• Lee Chang-Hyun

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title