Nonvolatile memory device and method for testing nonvolatile memory device using variable resistance material

Patent metadata

Field	Value
Publication number	US-9443582-B2
Application number	US-201414463376-A
Country	US
Kind code	B2
Filing date	Aug 19, 2014
Priority date	Nov 5, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.

First claim

What is claimed is:

1. A method for testing a nonvolatile memory device, the method comprising:
monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device;
determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level;
determining a number of first fail bits generated in the first resistance dispersion based on the lower test bias level and a number of second fail bits generated in the second resistance dispersion based on the upper test bias level;
determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits; and
trimming the reference bias level to the selected reference bias level,
wherein the lower test bias level is spaced apart by a first margin from the reference bias level, the upper test bias level is spaced apart by a second margin from the reference bias level, and the first margin and the second margin are different from each other.

2. The method for testing a nonvolatile memory device of claim 1 , wherein said trimming the reference bias level comprises trimming the reference bias level so that a sum of the number of the first fail bits and the number of the second fail bits is minimized.

3. The method for testing a nonvolatile memory device of claim 1 , wherein the first resistance dispersion and the second resistance dispersion are asymmetric with respect to each other.

4. The method for testing a nonvolatile memory device of claim 1 , wherein the first resistance dispersion and the second resistance dispersion correspond to set data and reset data, respectively, and the reference bias level is a level of a reference bias of a sense amplifier for reading the set data and the reset data.

5. The method for testing a nonvolatile memory device of claim 1 , wherein an absolute value of the selected reference bias level is larger than an absolute value of an average of a tail of the first resistance dispersion and a tail of the second resistance dispersion.

6. The method for testing a nonvolatile memory device of claim 1 , wherein an absolute value of the selected reference bias level is less than an absolute value of an average of a peak of the first resistance dispersion and a peak of the second resistance dispersion.

7. A method for testing a nonvolatile memory device, comprising:
monitoring a first resistance dispersion and a second resistance dispersion of the nonvolatile memory device;
determining first to n-th candidate reference bias levels, first to n-th upper test bias levels, and first to n-th lower test bias levels, wherein a k-th upper test bias level and a k-th lower test bias level are disposed on opposite sides of a k-th candidate reference bias level, where n is a natural number, and k is equal to or greater than 1 and equal to or less than n;
determining a number of first to n-th lower fail bits and a number of first to n-th upper fail bits using the first to n-th lower test bias levels and the first to n-th upper test bias levels, wherein a k-th lower fail bit is generated in the first resistance dispersion based on the k-th lower test bias level, and a k-th upper fail bit is generated in the second resistance dispersion based on the k-th upper test bias level;
determining first to n-th sums using the number of the first to n-th lower fail bits and the number of the first to n-th upper fail bits, wherein a k-th sum is calculated using a number of the k-th lower fail bits and a number of the k-th upper fail bits; and
determining a selected reference bias level among the first to n-th candidate reference bias levels, using the first to n-th sums,
wherein an absolute value of the selected reference bias level is less than an absolute value of an average of a peak of the first resistance dispersion and a peak of the second resistance dispersion.

8. The method for testing a nonvolatile memory device of claim 7 , wherein an m-th sum (where, m is a natural number that is equal to or greater than 1 and equal to or less than n) is a smallest sum among the first to n-th sums, and the selected reference bias level is an m-th candidate reference bias level that corresponds to the m-th sum.

9. The method for testing a nonvolatile memory device of claim 7 , wherein the k-th upper test bias level is spaced apart by a k-th upper margin from the k-th candidate reference bias level, the k-th lower test bias level is spaced apart by a k-th lower margin from the k-th candidate reference bias level, and the k-th upper margin and the k-th lower margin are different from each other.

10. The method for testing a nonvolatile memory device of claim 7 , wherein a g-th upper test bias level is spaced apart by a g-th upper margin from a g-th candidate reference bias level from among the first to n-th candidate reference bias levels, and a g-th lower test bias level is spaced apart by a g-th lower margin from the g-th candidate reference bias level, and
wherein the g-th upper margin and a (g+1)-th upper margin are equal to each other, the g-th lower margin and a (g+1)-th lower margin are equal to each other, and g is a natural number that is equal to or greater than 1 and equal to or less than n.

11. The method for testing a nonvolatile memory device of claim 7 , wherein a g-th upper test bias level is spaced apart by a g-th upper margin from a g-th candidate reference bias level from among the first to n-th candidate reference bias levels, and a g-th lower test bias level is spaced apart by a g-th lower margin from the g-th candidate reference bias level, and
wherein a gap between the g-th lower test bias level and the g-th upper test bias level is equal to a gap between a (g+1)-th lower test bias level and a (g+1)-th upper test bias level, and g is a natural number that is equal to or greater than 1 and equal to or less than n.

12. The method for testing a nonvolatile memory device of claim 7 , wherein the first resistance dispersion and the second resistance dispersion are asymmetric with respect to each other.

13. The method for testing a nonvolatile memory device of claim 7 , wherein the absolute value of the selected reference bias level is greater than an absolute value of an average of a tail of the first resistance dispersion and a tail of the second resistance dispersion.

14. A nonvolatile memory device, comprising:
a plurality of nonvolatile memory cells each configured to be selectively set and reset to store data therein;
a read circuit configured to read the stored data from the memory cells; and
a trimming circuit configured to supply a trimming signal to the read circuit to match a trimmed reference bias level of a reference bias which is employed by the read circuit to read the stored data from the memory cells,
wherein the trimmed reference bias level minimizes a weighted sum of a number of first fail bits and a number of second fail bits,
wherein the first fail bits are generated in a first resistance dispersion based on a lower test bias level disposed on a first side of the trimmed reference bias level,
wherein the second fail bits are generated in a second resistance dispersion based on an upper test bias level disposed on a second side of the trimmed reference bias level which is opposite the first side, and
wherein in the weighted sum the number of first fail bits is weighted by a first weight and the number of second fail bits is weighted by a second weight.

15. The nonvolatile memory device of claim 14 , wherein the second weight is different than the first weight.

16. The nonvolatile me

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Moon-Ki
• Lim Ki-Won

Classifications

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C29/50008

  of impedance · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title