Data processing apparatus and method for handling performance of a cache maintenance operation

Patent metadata

Field	Value
Publication number	US-9442856-B2
Application number	US-201514731437-A
Country	US
Kind code	B2
Filing date	Jun 5, 2015
Priority date	Jan 15, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.

First claim

We claim:

1. An apparatus comprising:
cache maintenance circuitry to perform a cache maintenance operation on a first level cache and an associated second level cache; wherein
when the cache maintenance operation performed on the first level cache causes data to be evicted from the first level cache, an indicator associated with the eviction is passed to the associated second level cache; and

access control circuitry to modify, in dependence on the indicator, an eviction handling operation performed on the associated second level cache in response to the eviction, such that the cache maintenance operation for the associated second level cache is incorporated within the eviction handling operation.

2. An apparatus as claimed in claim 1 , wherein:
the evicted data is passed to the associated second level cache with a corresponding address indication, and the access control circuitry, when performing said eviction handling operation, is arranged to use said corresponding address indication to perform a lookup within the second level cache to determine when a hit condition is detected, the hit condition identifying a cache line within the second level cache that is storing data associated with the corresponding address indication;
when the hit condition is detected, the access control circuitry, when performing the eviction handling operation, is arranged to update the cache line identified by the hit condition with the evicted data; and
when the evicted data has said indicator associated therewith, the access control circuitry is arranged to modify the eviction handling operation by additionally causing the evicted data to be placed in an eviction buffer associated with the associated second level cache, for subsequent eviction of the evicted data from the associated second level cache.

3. An apparatus as claimed in claim 2 , wherein:
when the evicted data does not have said indicator associated therewith, the access control circuitry is further arranged, when updating the cache line identified by the hit condition with the evicted data, to mark the cache line as valid and containing dirty data;
when the evicted data has said indicator associated therewith, the access control circuitry is arranged, when updating the cache line identified by the hit condition with the evicted data, to further modify the eviction handling operation by marking the cache line as valid but not containing dirty data.

4. An apparatus as claimed in claim 2 , wherein when the indicator identifies that the cache maintenance operation requires invalidation of the evicted data within the first level cache and the associated second level cache, then the access control circuitry is arranged to further modify the eviction handling operation by setting an invalid flag for the cache line identified by the hit condition instead of updating that cache line with the evicted data.

5. An apparatus as claimed in claim 2 , wherein:
said second level cache includes a store buffer in which the evicted data is temporarily stored until the eviction handling operation has been performed by the access control circuitry;
when the evicted data has said indicator associated therewith, the access control circuitry is arranged to cause the evicted data to be routed from the store buffer to the eviction buffer.

6. An apparatus as claimed in claim 2 , wherein:
when the hit condition is not detected, the access control circuitry is further arranged, when performing the eviction handling operation, to select a victim cache line from within the second level cache, to write the evicted data into the victim cache line, and to associate the corresponding address indication with that victim cache line.

7. An apparatus as claimed in claim 6 , wherein:
when the evicted data does not have said indicator associated therewith, the access control circuitry is further arranged, when performing the eviction handling operation, to mark the victim cache line as valid and containing dirty data;
when the evicted data has said indicator associated therewith, the access control circuitry is arranged to further modify the eviction handling operation by marking the victim cache line as valid but not containing dirty data.

8. An apparatus as claimed in claim 6 , wherein when current data stored in the victim cache line at the time of selection by the access control circuitry is marked as valid and dirty, that current data is routed to the eviction buffer prior to writing the evicted data into the victim cache line and associating the corresponding address indication with that victim cache line.

9. An apparatus as claimed in claim 1 , wherein:
said first level cache comprises a plurality of cache units, each cache unit being associated with a corresponding data processing unit amongst a plurality of data processing units; and
said second level cache is shared by said plurality of data processing units.

10. An apparatus as claimed in claim 9 , further comprising:
a snoop control unit coupled between the first level cache and the second level cache, to manage coherency of data within the cache units of the first level cache and the second level cache;
the snoop control unit, in response to evicted data output by one of said cache units of the first level cache, to output the evicted data to the second level cache, and further, when the evicted data resulted from performance of the cache maintenance operation, to output said indicator to the second level cache in association with the evicted data.

11. An apparatus as claimed in claim 1 , wherein said second level cache is integrated onto an integrated circuit that also provides data processing circuitry and said first level cache.

12. An apparatus as claimed in claim 1 , wherein:
when the cache maintenance required in respect of the first level cache during performance of the cache maintenance operation does not cause data to be evicted from the first level cache, the cache maintenance circuitry is configured to directly initiate the required cache maintenance in the second level cache.

13. An apparatus as claimed in claim 1 , wherein:
said indicator is encoded into a control signal passed to the second level cache in association with the evicted data;
the control signal is encoded with a value chosen from a first set of values to identify the indicator; and
the control signal is encoded with a value not in said first set of values to identify that there is no indicator.

14. An apparatus as claimed in claim 13 , wherein:
the control value is encoded with a first value chosen from said first set of values to identify that the associated evicted data has arisen from performance of a “clean” cache maintenance operation; and
the control value is encoded with a second value chosen from said first set of values to identify that the associated evicted data has arisen from performance of a “clean and invalidate” cache maintenance operation.

15. An apparatus as claimed in claim 14 , further comprising:
a third level cache;
further access control circuitry associated with the third level cache to perform, in response to data evicted from the second level cache, a further eviction handling operation requiring access to the third level cache;
when the evicted data from the first level cache has said indicator associated therewith, the access control circuitry associated with the second level cache is arranged to modify the eviction handling operation by additionally causing the evicted data to be placed in an eviction buffer associated with the second level cache, for subsequent eviction of the evicted data from the second level

Assignees

• Advanced Risc Mach Ltd

Inventors

• Grandou Gilles Eric
• Raphalen Philippe Jean-Pierre
• Mascheroni Andrea

Classifications

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0833 Primary

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title