Transmission channel for ultrasound applications

Patent metadata

Field	Value
Publication number	US-9442507-B2
Application number	US-201414573438-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a buffer with anti-memory circuitry to couple drains of the buffer transistors to voltage reference terminals during a clamping phase.

First claim

The invention claimed is:

1. A device, comprising:
a first half-bridge including:
a first buffer transistor having a first conduction terminal coupled to a first voltage reference terminal;
a first buffer diode coupled between a second conduction terminal of the first buffer transistor and a central buffer node;
a second buffer transistor having a first conduction terminal coupled to a second voltage reference terminal; and
a second buffer diode coupled between a second conduction terminal of the second buffer transistor and the central buffer node;

a second half-bridge including:
a third buffer transistor having a first conduction terminal coupled to a third voltage reference terminal;
a third buffer diode coupled between a second conduction terminal of the third buffer transistor and the central buffer node;
a fourth buffer transistor having a first conduction terminal coupled to a fourth voltage reference terminal; and
a fourth buffer diode coupled between a second conduction terminal of the fourth buffer transistor and the central buffer node; and

anti-memory circuitry configured to:
couple the second conduction terminal of the first buffer transistor to at least one of the second voltage reference terminal and the fourth voltage reference terminal;
couple the second conduction terminal of the second buffer transistor to at least one of the first voltage reference terminal and the third voltage reference terminal;
couple the second conduction terminal of the third buffer transistor to at least one of the second voltage reference terminal and the fourth voltage reference terminal; and
couple the second conduction terminal of the fourth buffer transistor to at least one of the first voltage reference terminal and the third voltage reference terminal.

2. The device of claim 1 wherein the anti-memory circuitry comprises:
a first switch coupled between the second conduction terminal of the first buffer transistor and the second voltage reference terminal;
a second switch coupled between the second conduction terminal of the third buffer transistor and the second voltage reference terminal;
a third switch coupled between the second conduction terminal of the second buffer transistor and the first voltage reference terminal; and
a fourth switch coupled between the second conduction terminal of the fourth buffer transistor and the first voltage reference terminal.

3. The device of claim 2 wherein,
the first buffer transistor is a P-MOS transistor and the second conduction terminal of the first buffer transistor is a drain of the first buffer transistor;
the second buffer transistor is an N-MOS transistor and the second conduction terminal of the second buffer transistor is a drain of the second buffer transistor;
the third buffer transistor is a P-MOS transistor and the second conduction terminal of the third buffer transistor is a drain of the third buffer transistor; and
the fourth buffer transistor is an N-MOS transistor and the second conduction terminal of the fourth buffer transistor is a drain of the fourth buffer transistor.

4. The device of claim 3 wherein,
the first voltage reference terminal is configured to couple to a first positive high-voltage reference;
the second voltage reference terminal is configured to couple to a first negative high-voltage reference;
the third voltage reference terminal is configured to couple to a second positive high-voltage reference; and
the fourth voltage reference terminal is configured to couple to a second negative high-voltage reference.

5. The device of claim 2 , comprising:
a controller configured to generate control signals to:
close the first, second, third and fourth switches during a clamping phase of operation; and
close the first, second, third and fourth switches during a receiving phase of operation.

6. The device of claim 5 wherein the controller is configured to generate control signals to:
close the first, second and fourth switches when the second buffer transistor is closed;
close the first, second and third switches when the fourth buffer transistor is closed;
close the second, third and fourth switches when the first buffer transistor is closed; and
close the first, third and fourth switches when the third buffer transistor is closed.

7. The device of claim 1 wherein the anti-memory circuitry comprises:
a first switch having a first conduction terminal coupled to the second voltage reference terminal;
a first control diode coupled between a second conduction terminal of the first switch and the second conduction terminal of the first buffer transistor;
a second control diode coupled between the second conduction terminal of the first switch and the second conduction terminal of the third buffer transistor;
a second switch having a first conduction terminal coupled to the fourth voltage reference terminal;
a third control diode coupled between a second conduction terminal of the second switch and the second conduction terminal of the first buffer transistor;
a fourth control diode coupled between the second conduction terminal of the second switch and the second conduction terminal of the third buffer transistor;
a third switch having a first conduction terminal coupled to the first voltage reference terminal;
a fifth control diode coupled between a second conduction terminal of the third switch and the second conduction terminal of the second buffer transistor;
a sixth control diode coupled between the second conduction terminal of the third switch and the second conduction terminal of the fourth buffer transistor;
a fourth switch having a first conduction terminal coupled to the third voltage reference terminal;
a seventh control diode coupled between a second conduction terminal of the fourth switch and the second conduction terminal of the second buffer transistor; and
an eighth control diode coupled between the second conduction terminal of the fourth switch and the second conduction terminal of the fourth buffer transistor.

8. The device of claim 7 wherein,
the first buffer transistor is a P-MOS transistor and the second conduction terminal of the first buffer transistor is a drain of the first buffer transistor;
the second buffer transistor is an N-MOS transistor and the second conduction terminal of the second buffer transistor is a drain of the second buffer transistor;
the third buffer transistor is a P-MOS transistor and the second conduction terminal of the third buffer transistor is a drain of the third buffer transistor; and
the fourth buffer transistor is an N-MOS transistor and the second conduction terminal of the fourth buffer transistor is a drain of the fourth buffer transistor.

9. The device of claim 1 wherein the anti-memory circuitry comprises:
a first resistor coupled between the second conduction terminal of the first buffer transistor and the second voltage reference terminal;
a second resistor coupled between the second conduction terminal of the third buffer transistor and the second voltage reference terminal;
a third resistor coupled between the second conduction terminal of the second buffer transistor and the first voltage reference terminal; and
a fourth resistor coupled between the second conduction terminal of the fourth buffer transistor and the first voltage reference terminal.

10. The device of claim 9 wherein,
the first buffer transistor is a P-MOS transistor and the second conduction terminal of the first buffer transistor is a drain of the first buffer transistor;
the second buffer transistor is an N-MOS transistor and the second conduction terminal of the second buffer transistor is a drain of the second buffer transis

Assignees

• St Microelectronics Srl

Inventors

• Ghisu Davide Ugo
• Rossi Sandro
• Bianchi Dario

Classifications

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• G05F3/02 Primary

  Regulating voltage or current · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title

• B06B1/0215 Primary

  for generating pulses, e.g. bursts of oscillations, envelopes · CPC title