Control of spectral agressors in a physiological signal montoring device

Patent metadata

Field	Value
Publication number	US-9439150-B2
Application number	US-201313862227-A
Country	US
Kind code	B2
Filing date	Apr 12, 2013
Priority date	Mar 15, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

This disclosure describes techniques for controlling spectral aggressors in a sensing device that uses a low power sleep mode to manage the power consumed by the device. In some examples, the techniques for controlling spectral aggressors may include configuring one or more of an algorithm processing rate for a processor, a buffering rate for the processor, a sampling rate for an analog-to-digital converter, an execution unit processing rate for the processor, and an algorithm subdivision factor for the processor such that spectral interference caused by a sleep cycle rate of the processor occurs outside of one or more target frequency bands of a sampled signal. The techniques of this disclosure may be used to reduce noise in a sensing system that uses a low power sleep mode to manage the power consumed by the device.

First claim

The invention claimed is:

1. A signal monitoring device comprising:
a power source;
a power distribution network electrically coupled to the power source;
an analog-to-digital converter electrically coupled to the power distribution network and configured to sample an input signal to produce a sampled signal; and
a processor electrically coupled to the power distribution network and configured to cycle between an algorithm processing mode and a sleep mode based on a sleep cycle rate,
wherein the sleep cycle rate causes spectral interference to propagate through the power distribution network and into the sampled signal via the analog-to-digital converter, and
wherein the sleep cycle rate further causes the spectral interference that is generated due to the sleep cycle rate to occur in the sampled signal at one or more frequencies that are outside of a target frequency band of the sampled signal.

2. The device of claim 1 , wherein the sleep cycle rate is configured such that the spectral interference caused by the sleep cycle rate occurs in the sampled signal at the one or more frequencies that are outside of the target frequency band of the sampled signal.

3. The device of claim 2 , wherein the sleep cycle rate is configured such that the sleep cycle rate is greater than an upper bound frequency of the target frequency band of the sampled signal.

4. The device of claim 2 , wherein the sleep cycle rate is configured such that the sleep cycle rate is less than a lower bound frequency of the target frequency band of the sampled signal.

5. The device of claim 1 ,
wherein the processor is further configured to invoke instances of a processing algorithm at an algorithm processing rate to process the sampled signal,
wherein the sleep cycle rate is configured to be equal to the algorithm processing rate, and
wherein the algorithm processing rate is configured such that the spectral interference caused by the sleep cycle rate occurs in the sampled signal at the one or more frequencies that are outside of the target frequency band of the sampled signal.

6. The device of claim 5 , wherein the algorithm processing rate is configured such that the sleep cycle rate is greater than an upper bound frequency of the target frequency band of the sampled signal or less than a lower bound frequency of the target frequency band of the sampled signal.

7. The device of claim 1 ,
wherein the analog-to-digital converter is a first analog-to-digital converter, wherein the input signal is a first input signal, wherein the sampled signal is a first sampled signal,
wherein the device further comprises a second analog-to-digital converter configured to sample a second input signal to produce a second sampled signal,
wherein the processor is further configured to invoke instances of a processing algorithm at an algorithm processing rate to process the second sampled signal,
wherein the sleep cycle rate is configured to be equal to the algorithm processing rate, and
wherein the algorithm processing rate is configured such that the spectral interference caused by the sleep cycle rate occurs in the first sampled signal at the one or more frequencies that are outside of the target frequency band of the first sampled signal.

8. The device of claim 7 , wherein the algorithm processing rate is configured such that the sleep cycle rate is greater than an upper bound frequency of the target frequency band of the first sampled signal or less than a lower bound frequency of the target frequency band of the first sampled signal.

9. The device of claim 1 ,
wherein the analog-to-digital converter is further configured to sample the input signal at a sampling rate,
wherein the processor is further configured to buffer the sampled signal at a buffering rate, the buffering rate being indicative of a number of data samples to buffer per invocation of a processing algorithm,
wherein the processor is further configured to invoke instances of the processing algorithm at a rate equal to a quotient of the sampling rate divided by the buffering rate to process the sampled signal,
wherein the sleep cycle rate is configured to be equal to the quotient of the sampling rate divided by the buffering rate, and
wherein the buffering rate and the sampling rate are configured such that the spectral interference caused by the sleep cycle rate occurs in the sampled signal at the one or more frequencies that are outside of the target frequency band of the sampled signal.

10. The device of claim 9 , wherein the buffering rate and the sampling rate are configured such that the sleep cycle rate is greater than an upper bound frequency of the target frequency band of the sampled signal or less than a lower bound frequency of the target frequency band of the sampled signal.

11. The device of claim 1 ,
wherein the analog-to-digital converter is a first analog-to-digital converter, wherein the input signal is a first input signal, wherein the sampled signal is a first sampled signal,
wherein the device further comprises a second analog-to-digital converter configured to sample a second input signal at a sampling rate to produce a second sampled signal,
wherein the processor is further configured to buffer the second sampled signal at a buffering rate, the buffering rate being indicative of a number of data samples to buffer per invocation of a processing algorithm,
wherein the processor is further configured to invoke instances of the processing algorithm at a rate equal to a quotient of the sampling rate divided by the buffering rate to process the second sampled signal,
wherein the sleep cycle rate is configured to be equal to the quotient of the sampling rate divided by the buffering rate, and
wherein the buffering rate and the sampling rate are configured such that the spectral interference caused by the sleep cycle rate occurs in the first sampled signal at the one or more frequencies that are outside of the target frequency band of the first sampled signal.

12. The device of claim 11 , wherein the buffering rate and the sampling rate are configured such that the sleep cycle rate is greater than an upper bound frequency of the target frequency band of the first sampled signal or less than a lower bound frequency of the target frequency band of the first sampled signal.

13. The device of claim 1 ,
wherein the processor is further configured to invoke instances of a processing algorithm at an algorithm processing rate to process the sampled signal,
wherein the processor is further configured to, for each of the instances of the processing algorithm that are invoked, execute the respective instance of the processing algorithm during a number of separate time intervals, each of the separate time intervals being separated from adjacent time intervals by a time interval where the respective processing algorithm is not executed, the number of separate time intervals being determined by an algorithm subdivision factor,
wherein the sleep cycle rate is configured to be equal to a product of an algorithm processing rate and the algorithm subdivision factor, and
wherein the algorithm processing rate and the algorithm subdivision factor are configured such that the spectral interference caused by the sleep cycle rate occurs in the sampled signal at the one or more frequencies that are outside of the target frequency band of the sampled signal.

14. The device of claim 13 , wherein the algorithm processing rate and the algorithm subdivision factor are configured such that the sleep cycle rate is greater than an upper bound frequency of the target frequency band of the sampled signal or l

Assignees

• Medtronic Inc

Inventors

• Carlson David L
• Stanslaski Scott R
• Cong Peng
• Denison Timothy J
• Linde David E
• Jensen Randy M

Classifications

• A61B5/374

  Detecting the frequency distribution of signals, e.g. detecting delta, theta, alpha, beta or gamma waves · CPC title

• A61B5/31

  for electroencephalography [EEG] · CPC title

• H04W52/0274

  by switching on or off the equipment or parts thereof · CPC title

• A61B5/7225

  Details of analogue processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation (input circuits for detecting, measuring, or recording bioelectric or biomagnetic signals A61B5/30; specific diagnostic methods using bioelectric or biomagnetic signals A61B5/316) · CPC title

• H04W52/0238 Primary

  where the received signal is an unwanted signal, e.g. interference or idle signal · CPC title