Apparatus and method for motion estimation for variable block sizes

Patent metadata

Field	Value
Publication number	US-9438927-B2
Application number	US-201414218488-A
Country	US
Kind code	B2
Filing date	Mar 18, 2014
Priority date	Apr 11, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A motion estimation apparatus and method are disclosed. The motion estimation apparatus includes processing element (PE) array units, sub-SAD calculation units, motion vector calculation units, and a minimum motion vector selector. The PE array units each perform parallel processing for each of the three types of coding units. The sub-SAD calculation units calculate respective SAD values for the three types of coding units. The motion vector calculation units calculate respective motion vectors for the three types of coding units. The minimum motion vector selector selects a minimum motion vector from among the motion vectors.

First claim

What is claimed is:

1. A motion estimation apparatus, comprising:
circuitry configured to
perform parallel processing for each of three types of coding units via a processing element (PE) array unit;
calculate respective SAD values for the three types of coding units via a sub-SAD calculation unit;
calculate respective motion vectors for the three types of coding units via a motion vector calculation unit; and
select a minimum motion vector from among the motion vectors via a minimum motion vector selector,
wherein the three types of coding units comprise:
an N×N block type including 64×64, 32×32, 16×16, and 8×8 block sizes;
a 2N×N block type including 64×32, 32×16, 16×8, and 8×4 block sizes; and
an N×2N block type including 32×64, 16×32, 8×16, and 4×8 block sizes,

wherein the motion estimation apparatus supports 12 block sizes that are supported in an HEVC standard,
wherein processing of four block sizes corresponding to each of the three types of coding units is performed with hardware shared, and
wherein the PE array unit comprises an N×N array, a 2N×N PE array, and an N×2N PE array.

2. The motion estimation apparatus of claim 1 , wherein the sub-SAD calculation unit comprises an N×N sub-SAD calculator, a 2N×N sub-SAD calculator, and an N×2N sub-SAD calculator.

3. The motion estimation apparatus of claim 2 , wherein the N×N PE array, the 2N×N PE array and the N×2N PE array comprise 16 processing elements (PEs).

4. The motion estimation apparatus of claim 3 , wherein the each of PEs alternatively receives an odd current data input and an even current data input so that internal processing speed is twice data input speed.

5. The motion estimation apparatus of claim 4 , further comprising:
current image storage memory configured to store a current image;
previous image storage memory configured to store a previous image; and
an address generator configured to generate a memory address required for motion estimation in response to control of a control unit.

6. A motion estimation method, comprising:
calculating respective SAD values for three types of coding units by performing parallel processing for each of the three types of coding units;
calculating respective motion vectors for the three types of coding units; and
selecting a minimum motion vector from among the motion vectors,
wherein the three types of coding units comprise:
an N×N block type including 64×64, 32×32, 16×16, and 8×8 block sizes;
a 2N×N block type including 64×32, 32×16, 16×8, and 8×4 block sizes; and
an N×2N block type including 32×64, 16×32, 8×16, and 4×8 block sizes,

wherein the motion estimation method supports 12 block sizes that are supported in an HEVC standard,
wherein processing of four block sizes corresponding to each of the three types of coding units is performed with hardware shared, and
wherein calculating the SAD values is performed using PEs, each of which alternatively receives an odd current data input and an even current data input so that internal processing speed is twice data input speed.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Park Seong-Mo
• Byun Kyung-Jin
• Eum Nak-Woong

Classifications

• H04N19/436

  using parallelised computational arrangements · CPC title

• H04N19/52 Primary

  by predictive encoding · CPC title

• H04N19/42

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title