Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

Patent metadata

Field	Value
Publication number	US-9438424-B2
Application number	US-201414458592-A
Country	US
Kind code	B2
Filing date	Aug 13, 2014
Priority date	Apr 8, 2004
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A secure demand paging system ( 1020 ) includes a processor ( 1030 ) operable for executing instructions, an internal memory ( 1034 ) for a first page in a first virtual machine context, an external memory ( 1024 ) for a second page in a second virtual machine context, and a security circuit ( 1038 ) coupled to the processor ( 1030 ) and to the internal memory ( 1034 ) for maintaining the first page secure in the internal memory ( 1034 ). The processor ( 1030 ) is operable to execute sets of instructions representing: a central controller ( 4210 ), an abort handler ( 4260 ) coupled to supply to the central controller ( 4210 ) at least one signal representing a page fault by an instruction in the processor ( 1030 ), a scavenger ( 4220 ) responsive to the central controller ( 4210 ) and operable to identify the first page as a page to free, a virtual machine context switcher ( 4230 ) responsive to the central controller ( 4210 ) to change from the first virtual machine context to the second virtual machine context; and a swapper manager ( 4240 ) operable to swap in the second page from the external memory ( 1024 ) with decryption and integrity check, to the internal memory ( 1034 ) in place of the first page.

First claim

What is claimed is:

1. A secure demand paging (SPD) system comprising:
an external volatile memory;
a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor is operable to:
execute at least one protected application in the secure internal memory;
execute a client application at intervals and also have at least one interval of lower-activity status;
selectively perform the page scavenging so that page wiping is included and a swap out of a modified wiped page is deferred; and
establish a queue identifying pages for which swap out is deferred; and

a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the page scavenger for said at least one interval of lower-activity status.

2. The system claimed in claim 1 wherein said microprocessor is operable to subsequently swap out pages in response to the queue identifying pages for which swap out is deferred.

3. A secure demand paging (SDP) system comprising:
an external volatile memory;
a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor is operable to:
execute at least one protected application in the secure internal memory;
execute a client application at intervals and also have at least one interval of lower-activity status; and
preform a virtual machine context switch to load a protected application, run the protected application, and execute the page scavenger; and

a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the page scavenger for said at least one interval of lower-activity status.

4. The system claimed in claim 3 wherein said processor is operable to selectively perform the page scavenging so that a swap out is included and a swap in is bypassed.

5. The system claimed in claim 3 wherein said processor is operable to selectively perform the page scavenging so that page wiping is included and a swap out of a modified wiped page is deferred.

6. The system claimed in claim 3 wherein the page scavenger includes a priority for wiping out a page.

7. The system claimed in claim 6 wherein the page scavenger includes a subsequent page swapping out operation.

8. The system claimed in claim 3 wherein said page scavenger is scheduled for an interval preceded by an interval for execution of the protected application.

9. The system claimed in claim 3 wherein said microprocessor is operable to perform a first call to the page scavenger during a busier interval when the secure internal memory is full for paging purposes, and a second call to page scavenger during said at least one interval of lower activity status.

10. A secure demand paging (SDP) system comprising:
an external volatile memory;
a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor is operable to:
execute at least one protected application in the secure internal memory;
execute a client application at intervals and also have at least one interval of lower-activity status; and
perform a virtual machine context activation during an interval of lower-activity status; and

a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the page scavenger for said at least one interval of lower-activity status.

11. A secure demand paging (SDP) system comprising:
an external volatile memory;
a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor is operable to:
execute at least one protected application in the secure internal memory;
execute a client application at intervals and also have at least one interval of lower-activity status; and
perform a virtual machine context deactivation during an interval of lower-activity status; and

a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the page scavenger for said at least one interval of lower-activity status.

12. A process for providing a secure demand paging (SDP) system comprising:
providing an external volatile memory;
providing a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor operable to:
execute at least one protected application in the secure internal memory;
execute a client application at intervals and also have at least one interval of lower-activity status;
selectively perform page scavenging so that page wiping is included and a swap out of a modified wined page is deferred;
establish a queue identifying pages for which swap out is deferred; and

providing a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the pane scavenger for said at least one interval of lower-activity status.

13. The process claimed in claim 12 wherein said processor is operable to subsequently swap out pages in response to the queue identifying pages for which swap out is deferred.

14. The process claimed in claim 12 wherein the page scavenger includes a priority for wiping out a page.

15. The process claimed in claim 14 wherein the page scavenger includes a subsequent page swapping out operation.

16. The process claimed in claim 12 wherein said page scavenger is scheduled for an interval preceded by an interval for execution of the protected application.

17. A process for providing a secure demand paging (SDP) system comprising:
providing an external volatile memory;
providing a microprocessor coupled to said external volatile memory, said microprocessor having a secure internal memory having a physical address space, and said microprocessor operable to:
execute at least one protected application in the secure internal memory;
execute a client application at intervals and also have at least one interval of lower-activity status; and
perform a virtual machine context switch to load a protected application, run the protected application, and execute the page scavenger; and

providing a non-volatile memory storing a coded physical representation of operations accessible by said microprocessor including a representation of an SDP protected application including a page scavenger, and an operation to schedule the page scavenger for said at least one interval of lower-activity status.

18. The process in claim 17 wherein said processor is operable to selectively perform the page scavenging so that a swap out is included and a swap in is bypassed.

19. The process claimed in claim 17 wherein said processor is operable to selectively perform the pag

Assignees

• Texas Instruments Inc

Inventors

• Goss Steven
• Conti Gregory Remy Philippe
• Shankar Narendar M
• Akkar Mehdi-Laurent
• Vial Aymeric

Classifications

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• H04L63/123

  received data contents, e.g. message integrity · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• H04L63/20

  for managing network security; network security policies in general (filtering policies H04L63/0227) · CPC title