System and method for clocking integrated circuit

Patent metadata

Field	Value
Publication number	US-9438217-B2
Application number	US-201414337244-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Jul 22, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A system and method of clocking an integrated circuit (IC) includes determining operating characteristics of the IC. The IC has multiple domains and each domain receives a respective domain clock signal. A skew value is determined for each of the domain clock signals, where each skew value is associated with a respective domain of the IC. The domain clock signals are generated from a reference clock signal and each domain clock signal is skewed from the reference clock according to the respective skew value.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a plurality of domains each provided with one of a plurality of domain clock signals, wherein components of the integrated circuit within each domain are responsive to the provided one of the domain clock signals;
a control module for determining a skew value for each of the plurality of domain clock signals; and
a clock module for receiving a reference clock signal and generating the plurality of domain clock signals using the reference clock signal, wherein each domain clock signal is skewed from the reference clock according to the respective skew value,
wherein the control module monitors peak current at one or more locations in the integrated circuit and changes the skew value for at least some of the domains of the integrated circuit in response to a determination of excessive peak current at one or more locations in the integrated circuit.

2. The integrated circuit of claim 1 , further comprising a memory for maintaining a plurality of skew values for each of the domains of the integrated circuit, wherein the control module determines the skew value by selecting the skew value according to one or more operating characteristics of the integrated circuit.

3. The integrated circuit of claim 2 , wherein the operating characteristics include one or both of an operating frequency and an operating voltage of the integrated circuit.

4. The integrated circuit of claim 1 , wherein the control module changes the skew value for at least some of the domains, and determines whether a performance of the integrated circuit meets one or more performance criteria.

5. The integrated circuit of claim 1 , wherein the clock module comprises:
a plurality of buffers for delaying the reference clock signal by a phase shift; and
a selector for selecting one of the representations for each domain clock signal according to the skew value for the respective domain.

6. The integrated circuit of claim 1 , wherein the control module determines whether the integrated circuit meets one or more operation constraints based on the changed skew values.

7. The integrated circuit of claim 1 , wherein the skew values are increased in response to a determination of excessive peak current at one or more locations in the integrated circuit.

8. The integrated circuit of claim 2 , wherein the control module changes the operating frequency of the integrated circuit in response to a determination of excessive peak current at one or more locations in the integrated circuit and a determination that a predetermined number of times of changing the skew values has been reached.

Assignees

• Kannan Narayanan
• Srivastava Rohit
• Freescale Semiconductor Inc

Inventors

• Kannan Narayanan
• Srivastava Rohit

Classifications

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title