Low voltage and high driving charge pump

Patent metadata

Field	Value
Publication number	US-9438103-B2
Application number	US-201514595287-A
Country	US
Kind code	B2
Filing date	Jan 13, 2015
Priority date	Feb 29, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages.

First claim

What is claimed is:

1. A method of operating a charge pump circuit, comprising:
providing a plurality of diode devices in series, such that a first diode device is coupled to a second diode device;
providing a first two-phase output signal from an output of a first voltage multiplier circuit to a gate of a transistor, which has a source connected to a voltage source configured to provide a supply voltage and a drain connected to the first diode device;
providing an inverted version of an input clock signal to a first input of a second voltage multiplier circuit configured to generate a second two-phase output signal; and
providing the first two-phase output signal to a second input of the second voltage multiplier circuit.

2. The method of claim 1 ,
wherein the plurality of diode devices comprise a plurality of diode connected NMOS transistors coupled in series, such that a drain of a first diode connected NMOS transistor is coupled to a source of a second diode connected NMOS transistor; and
wherein the drain of the transistor is coupled to the first diode connected NMOS transistor.

3. The method of claim 2 , providing the second two-phase output signal from an output of the second voltage multiplier circuit to a second electrode of a first capacitor having a first electrode connected between the drain of the transistor and the first diode connected NMOS transistor.

4. The method of claim 3 , further comprising:
providing the first two-phase output signal from the output of the first voltage multiplier circuit to a second electrode of a second capacitor having a first electrode connected between the drain of the first diode connected NMOS transistor and the source of the second diode connected NMOS transistor.

5. The method of claim 3 , wherein the second two-phase output signal has a voltage value equal to twice the supply voltage during a first clock phase, a voltage value equal to zero during a second clock phase, and a voltage value equal to twice the supply voltage during a third clock phase.

6. The method of claim 5 , further comprising:
providing the input clock signal to a first input of the first voltage multiplier circuit; and
providing the second two-phase output signal to a second input of the first voltage multiplier circuit.

7. The method of claim 3 , further comprising:
providing an input signal to a first voltage doubler inverter configured to generate an inverted input signal;
providing the inverted input signal to a second voltage doubler inverter configured to output the input signal to a first electrode of a voltage doubler capacitor;
providing a supply voltage to a source of a voltage doubler transistor, which has a drain coupled to a second electrode of the voltage doubler capacitor;
providing the inverted input signal to a CMOS inverter configured to connect an output node of a voltage multiplier circuit to either a ground terminal or the voltage doubler capacitor based the inverted input signal; and
providing the supply voltage to a drain of a diode connected transistor, which has a source coupled to the CMOS inverter, the drain of the voltage doubler transistor, and the second electrode of the voltage doubler capacitor.

8. The method of claim 7 ,
wherein the CMOS inverter is configured to connect the output node of the voltage multiplier circuit to the ground terminal when the input signal causes charges to accumulate on the voltage doubler capacitor; and
wherein the CMOS inverter is configured to connect the output node of the voltage multiplier circuit to the voltage doubler capacitor when the input signal causes charges to be driven off of the voltage doubler capacitor.

9. The method of claim 1 , wherein the first two-phase output signal has a voltage value equal to zero during a first clock phase and a voltage value greater than or equal to the supply voltage during a second subsequent clock phase.

10. The method of claim 1 , wherein the input clock signal has a voltage value equal to zero during a first clock phase and a voltage value equal to the supply voltage during a second clock phase.

11. A method of operating a charge pump circuit, comprising:
providing a supply voltage to a drain of a first diode device, which has a source connected to a drain of a second diode device;
providing an input clock signal to a first input of a first voltage multiplier circuit;
providing a second two-phase output signal, which has a maximum value in alternating clock phases that is greater than a supply voltage, from a second voltage multiplier circuit to a second input of the first voltage multiplier circuit;
providing a first two-phase output signal from an output of the first voltage multiplier circuit to a gate of a transistor having a source coupled to a voltage source configured to provide the supply voltage and a drain coupled to the first diode device, wherein the first two-phase output signal has a maximum voltage in alternating clock phases that is sufficient to form a channel extending between a source of the transistor and a drain of the transistor;
providing a first input signal to a first input of the second voltage multiplier circuit, wherein the first input signal is equal to an inverted version of the input clock signal; and
providing the first two-phase output signal to a second input of the second voltage multiplier circuit.

12. The method of claim 11 ,
wherein the first input signal has a voltage value equal to zero during a first clock phase and a voltage value equal to the supply voltage during a second subsequent clock phase.

13. The method of claim 11 , further comprising:
providing an input signal to a first voltage doubler inverter configured to generate an inverted input signal;
providing the inverted input signal to a second voltage doubler inverter configured to output the input signal to a first electrode of a voltage doubler capacitor;
providing a supply voltage to a source of a voltage doubler transistor, which has a drain coupled to a second electrode of the voltage doubler capacitor;
providing the inverted input signal to a CMOS inverter configured to connect an output node of a voltage multiplier circuit to either a ground terminal or the voltage doubler capacitor based the inverted input signal; and
providing the supply voltage to a drain of a diode connected transistor, which has a source coupled to the CMOS inverter, the drain of the voltage doubler transistor, and the second electrode of the voltage doubler capacitor.

14. The method of claim 11 , wherein the second two-phase output signal has a voltage value equal to twice the supply voltage during a first clock phase, a voltage value equal to zero during a second clock phase, and a voltage value equal to twice the supply voltage during a third clock phase.

15. A method of operating a charge pump circuit, comprising:
providing a supply voltage to a first diode device connected to a second diode device;
providing an input clock signal to a first input of a first voltage multiplier circuit having a diode connected transistor;
providing a second two-phase output signal, which has a maximum value in alternating clock phases that is greater than a supply voltage, from a second voltage multiplier circuit to a second input of the first voltage multiplier circuit; and
providing a first two-phase output signal from an output of the first voltage multiplier circuit to a gate of a transistor having a source coupled to a voltage source configured to provide the supply voltage and a drain coupled to the first diode device.

16. The method of claim 15 , wherein the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Siao Yuan-Long

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• Y10T29/49117

  Conductor or circuit manufacturing · CPC title

• H02M2003/076

  Electricity · mapped topic

• H02M2003/078

  Electricity · mapped topic