Gate Structure and Method for Fabricating the Same
US-2015372149-A1 · Dec 24, 2015 · US
US9437751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9437751-B2 |
| Application number | US-201414555040-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 26, 2014 |
| Priority date | Dec 19, 2013 |
| Publication date | Sep 6, 2016 |
| Grant date | Sep 6, 2016 |
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A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate and including linkers to be bonded to metal ions metallic nanoparticles formed out of the metal ions over the linker layer and a nitride filling gaps between the metallic nanoparticles.
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a non-volatile memory device, comprising: forming a tunneling layer over a substrate; and forming a charge trapping layer over the tunneling layer, wherein the forming of the charge trapping layer comprises: forming a linker layer, which includes linkers, over the tunneling layer; forming metal ions over the linker layer; forming metallic nanoparticles by growing from the metal ions; and forming a nitride over the metallic…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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