Thin film transistor with multiple oxide semiconductor layers

Patent metadata

Field	Value
Publication number	US-9437747-B2
Application number	US-201514873279-A
Country	US
Kind code	B2
Filing date	Oct 2, 2015
Priority date	Jun 15, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first insulating layer;
a first oxide semiconductor layer over the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer; and
a second insulating layer over the third oxide semiconductor layer,
wherein the second oxide semiconductor layer comprises In, Ga, and Zn,
wherein the second oxide semiconductor layer has higher conductivity than the third oxide semiconductor layer and the first oxide semiconductor layer,
wherein the first oxide semiconductor layer has tapered side surfaces,
wherein the second oxide semiconductor layer has tapered side surfaces, and
wherein the third oxide semiconductor layer is in contact with the tapered side surfaces of the second oxide semiconductor layer.

2. A semiconductor device comprising:
a first insulating layer;
a first oxide semiconductor layer over the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer; and
a second insulating layer over the third oxide semiconductor layer,
wherein the second oxide semiconductor layer comprises In, Ga, and Zn,
wherein the second oxide semiconductor layer has a smaller thickness than the first oxide semiconductor layer and the third oxide semiconductor layer,
wherein the first oxide semiconductor layer has tapered side surfaces,
wherein the second oxide semiconductor layer has tapered side surfaces, and
wherein the third oxide semiconductor layer is in contact with the tapered side surfaces of the second oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the third oxide semiconductor layer is in contact with the tapered side surfaces of the first oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer has a larger thickness than the second oxide semiconductor layer and the third oxide semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer has a higher nitrogen, boron, or phosphorus concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

6. The semiconductor device according to claim 1 , further comprising:
a source electrode layer in contact with the third oxide semiconductor layer; and
a drain electrode layer in contact with the third oxide semiconductor layer.

7. The semiconductor device according to claim 1 , further comprising:
a first gate electrode layer below the first insulating layer; and
a second gate electrode layer over the second insulating layer.

8. The semiconductor device according to claim 1 , wherein a taper angle formed by the tapered side surface of the first oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10° and less than or equal to 60°.

9. The semiconductor device according to claim 1 , wherein a taper angle formed by the tapered side surface of the second oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10° and less than or equal to 60°.

10. The semiconductor device according to claim 1 , wherein a taper angle formed by the tapered side surface of the third oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10° and less than or equal to 60°.

11. The semiconductor device according to claim 2 , wherein the third oxide semiconductor layer is in contact with the tapered side surfaces of the first oxide semiconductor layer.

12. The semiconductor device according to claim 2 , wherein the second oxide semiconductor layer has a higher nitrogen, boron, or phosphorus concentration than the third oxide semiconductor layer and the first oxide semiconductor layer.

13. The semiconductor device according to claim 2 , further comprising:
a source electrode layer in contact with the third oxide semiconductor layer; and
a drain electrode layer in contact with the third oxide semiconductor layer.

14. The semiconductor device according to claim 2 , further comprising:
a first gate electrode layer below the first insulating layer; and
a second gate electrode layer over the second insulating layer.

15. The semiconductor device according to claim 2 , wherein a taper angle formed by the tapered side surface of the first oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10° and less than or equal to 60°.

16. The semiconductor device according to claim 2 , wherein a taper angle formed by the tapered side surface of the second oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10° and less than or equal to 60°.

17. The semiconductor device according to claim 2 , wherein a taper angle formed by the tapered side surface of the third oxide semiconductor layer and a surface of the first insulating layer is greater than or equal to 10° and less than or equal to 60°.

Assignees

• Semiconductor Energy Lab
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D62/80

  characterised by the materials · CPC title

• H10D30/615

  comprising a MOS gate electrode and at least one non-MOS gate electrode · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title