Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

Patent metadata

Field	Value
Publication number	US-9437706-B2
Application number	US-201414552959-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Dec 19, 2008
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A microelectronic device may be formed with at least one transistor having a source region and a drain region, wherein an interlayer dielectric layer may be formed adjacent the transistor. A trench may be formed through the first interlayer dielectric layer to at least one of the source region and the drain region and a conductive contact may be formed in the trench, wherein the conductive contact comprises a conformal conductive layer separated from the at least one of the source region and the drain region by a conformal insulating layer.

First claim

What is claimed is:

1. A device, comprising:
a transistor with a source region and a drain region;
an interlayer dielectric layer adjacent the transistor;
a trench through the first interlayer dielectric layer to at least one of the source region and the drain region;
a conductive contact in the trench, the conductive contact being separated from the at least one of the source region and the drain region by a conformal insulating layer, wherein the conductive contact comprises a conformal conductive layer;
a second interlayer dielectric layer;
a first metallization layer adjacent the second interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines;
a third interlayer dielectric layer over the second interlayer dielectric layer;
a second metallization layer adjacent the third interlayer dielectric layer and having a plurality of conductive vias and a plurality of conductive lines; and
wherein at least some of the plurality of conductive vias and the plurality of conductive lines of the first metallization layer and at least some of the plurality of conductive vias and the plurality of conductive lines of the second metallization layer are conductively connected to the conductive contact.

2. The device of claim 1 , wherein the conductive contact further comprises a conductive fill material on the conformal conductive layer and substantially filling the trench.

3. The device of claim 1 , wherein the transistor is a multigate transistor including a fin.

4. The device of claim 3 , wherein the conformal insulating layer is on a top surface and side walls of the fin.

5. The device of claim 1 , wherein the conformal insulating layer has a thickness of about 4 nanometers or less.

6. The device of claim 1 , wherein the conductive contact conformal conductive layer has a thickness of less than 100 nanometers.

7. The device of claim 1 , wherein the transistor is a P-type transistor and the conductive contact comprises a metal with a workfunction above about 5 eV.

8. The device of claim 1 , wherein the transistor is an N-type transistor and the conductive contact comprises a metal with a workfunction below about 3.2 eV.

9. The device of claim 1 , wherein the conductive contact conformal conductive layer comprises aluminum or nickel.

10. The device of claim 1 , wherein the transistor has a channel region that comprises a group III-V material.

11. The device of claim 1 , wherein the conformal insulating layer comprises hafnium oxide.

Assignees

• Intel Corp

Inventors

• Mukherjee Niloy
• Dewey Gilbert
• Metz Matthew V
• Kavalieros Jack T
• Chau Robert S

Classifications

• H10P14/42

  using a gas or vapour · CPC title

• H10D64/0111

  to Group IV semiconductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title