Method and structure for FinFET device

Patent metadata

Field	Value
Publication number	US-9437683-B2
Application number	US-201514959821-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Apr 16, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

First claim

What is claimed is:

1. A fin-like field-effect transistor (FinFET) device comprising:
a substrate having a fin-like field-effect transistor (FET) region;
first source/drain (S/D) regions, separated by a first gate region in the FET region;
a first high-k/metal gate (HK/MG) in the first gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial silicon (Si) layer as its upper portion;
an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion; and
the substrate as its bottom portion; and
a first S/D feature on top of the first fin structure, having a recessed Si layer, in the first S/D region, the first S/D feature including: a Si:C layer as its lower portion; and a Si:P layer as its upper portion.

2. The device of claim 1 , wherein the FET region is doped n-type (NFET region), and wherein the first fin structures includes:
a first semiconductor material layer epitaxially grown over the substrate; and
a second semiconductor material layer epitaxially grown on top of the first semiconductor material layer;
wherein the second and the first semiconductor material layers form the first fin structure; and
wherein the second semiconductor material layer is the upper portion of the first fin structure, the first semiconductor material layer is the middle portion of the first fin structure and the substrate is a bottom portion of the first fin structure.

3. The device of claim 2 , wherein the first HK/MG wraps over the second semiconductor material layer of the first fin structure.

4. The device of claim 2 , wherein the first S/D features includes:
the first semiconductor S/D feature epitaxially grown on top of a recess in the second semiconductor material layer.

5. The device of claim 4 , wherein the first semiconductor S/D feature includes a lower portion including a first dopant, and an upper portion including a second dopant, different from the first dopant.

6. The device of claim 2 , further comprising:
a dielectric isolation layer between the first fin structures in the NFET region and a second fin structures in a second region.

7. A fin-like field-effect transistor (FinFET) device comprising:
a substrate having a fin-like field-effect transistor (FET) region;
source/drain (S/D) regions, separated by a gate region in the FET region;
a HK/MG in the gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial SiGe layer as its upper portion;
an epitaxial Si layer as it upper middle portion;
an epitaxial SiGe layer as its lower middle portion; and
the substrate as its bottom portion; and
SiGeB S/D features on top of the first fin structure, having a recessed SiGe layer, in a first S/D region.

8. The device of claim 7 , wherein the FET region is doped p-type (PFET region), and wherein the first fin structures includes a first semiconductor material layer on top of the recessed SiGe layer.

9. The device of claim 8 , wherein the HK/MG wraps over the recessed SiGe layer of the first fin structure.

10. The device of claim 8 , wherein forming the S/D features are epitaxially grown on top of the recessed SiGe layer.

11. The device of claim 10 , wherein the SiGeB S/D features are doped with a first dopant.

12. A fin-like field-effect transistor (FinFET) device comprising:
a substrate having an n-type fin-like field-effect transistor (NFET) region and a p-type fin-like field-effect transistor (PFET) region;
first source/drain (S/D) regions, separated by a first gate region in the NFET region;
second source/drain (S/D) regions, separated by a second gate region in the NFET region;
a first high-k/metal gate (HK/MG) in the first gate region, including wrapping over an upper portion of a first fin structure, the first fin structure including:
an epitaxial silicon (Si) layer as its upper portion;
an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion; and
the substrate as its bottom portion;

a second HK/MG in the second gate region, including wrapping over an upper portion of a second fin structure, the second fin structure including:
an epitaxial SiGe layer as its upper portion;
an epitaxial Si layer as it upper middle portion;
an epitaxial SiGe layer as its lower middle portion; and
the substrate as its bottom portion;

a first S/D feature on top of the first fin structure, having a recessed Si layer, in the first S/D region, the first S/D feature including:
a Si:C layer as its lower portion; and
a Si:P layer as its upper portion; and

a SiGeB S/D features on top of the second fin structure, having a recessed SiGe layer, in the second S/D region.

13. The device of claim 12 , wherein:
the upper portion of the first fin structure, the Si layer, has a width in a range of about 4 nm to about 10 nm and a thickness in a range of about 20 nm to about 40 nm;
the middle portion of the first fin structure, the SiGe layer, has a thickness in a range of about 20 nm to about 90 nm and a Ge composition (in atomic percent) in a range of about 30% to about 80%;
the SiGeO feature has a thickness in a range of about 3 nm to about 10 nm;
the upper portion of the second fin structure, the SiGe layer, has a thickness in a range of about 20 nm to about 40 nm and a Ge composition (in atomic percent) in a range of about 45% to about 100%;
a remaining thickness of the recessed Si layer in the first fin structure is in a range of about 3 nm to about 10 nm;
the Si:C layer has a thickness in a range of about 5 nm to about 15 nm and a C composition (in atomic percent) in a range of about 0.5% to about 1.5%;
the Si:P layer has a thickness in a range of about 20 nm to about 35 nm;
a remaining thickness of the recessed SiGe layer in the second fin structure is in a range of about 3 nm to about 10 nm; and
the SiGeB layer has a thickness in a range of about 20 nm to about 35 nm and a Ge composition (in atomic percent) in a range of about 60% to about 100%.

14. The device of claim 12 , wherein the first fin structures includes:
a first semiconductor material layer epitaxially grown over the substrate; and
a second semiconductor material layer epitaxially grown on top of the first semiconductor material layer;
wherein the second and the first semiconductor material layers form the first fin structure; and
wherein the second semiconductor material layer is the upper portion of the first fin structure, the first semiconductor material layer is the middle portion of the first fin structure and the substrate is a bottom portion of the first fin structure.

15. The device of claim 12 , wherein the second fin structure in the PFET region includes:
a third semiconductor material layer epitaxially grown on top of the recessed second semiconductor material layer.

16. The device of claim 15 , wherein the first HK/MG wraps over the second semiconductor material layer of the first fin structure.

17. The device of claim 16 , wherein the second HK/MG wraps over the third semiconductor material layer of the second fin structure.

18. The device of claim 12 , wherein forming the first S/D features includes the first S/D feature epitaxially grown on top of a recess in the second semiconductor material layer.

19. The device of claim 18 , further comprising:
a first dopant in a lower portion of the first S/D feature; and
a second dopant in

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ching Kuo-Cheng
• Fung Ka-Hing
• Chang Chih-Sheng
• Wu Zhiqiang

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title