CMOS compatible thermopile with low impedance contact

Patent metadata

Field	Value
Publication number	US-9437652-B2
Application number	US-201414292281-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate comprising silicon-based semiconductor material having a top surface;
field oxide in isolation trenches in the substrate, the field oxide providing lateral isolation between active areas of the integrated circuit;
an area for complementary metal oxide semiconductor (CMOS) transistors comprising:
an n-channel metal oxide semiconductor (NMOS) transistor;
a p-channel metal oxide semiconductor (PMOS) transistor; and
a plurality of contacts on source and drain regions of the NMOS transistor and the PMOS transistor, the contacts having lateral aspect ratios of 1:1 to 1.5:1 at the top surface of the substrate; and

an embedded thermoelectric device comprising:
n-type thermoelectric elements in a plurality of the active areas, the n-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
p-type thermoelectric elements in a plurality of the active areas, the p-type thermoelectric elements being less than 300 nanometers wide at a narrowest position;
a plurality of stretch contacts on the n-type thermoelectric elements and the p-type thermoelectric elements, the stretch contacts having lateral aspect ratios greater than 4:1 at the top surface of the substrate, wherein the stretch contacts and the contacts have a common layer structure; and
a plurality of interconnects of metal levels and vias of via levels of the integrated circuit connecting the stretch contacts to a thermal node.

2. The integrated circuit of claim 1 , wherein the stretch contacts and the contacts include a liner comprising titanium and a fill metal comprising tungsten on the liner.

3. The integrated circuit of claim 1 , wherein the stretch contacts and the contacts include a first liner of titanium, a second liner of titanium nitride on the first liner and a fill metal comprising tungsten on the second liner.

4. The integrated circuit of claim 1 , wherein a width of the stretch contacts is substantially equal to a width of the contacts, and is less than a width of the n-type thermoelectric elements and the p-type thermoelectric elements at the top surface of the substrate.

5. The integrated circuit of claim 1 , wherein a width of the stretch contacts is greater than a width of the contacts, and is substantially equal to a width of the n-type thermoelectric elements and the p-type thermoelectric elements at the top surface of the substrate.

6. The integrated circuit of claim 1 , wherein a width of the stretch contacts is greater than a width of the contacts, and is greater than a width of the n-type thermoelectric elements and the p-type thermoelectric elements at the top surface of the substrate.

7. The integrated circuit of claim 1 , wherein the n-type thermoelectric elements and the p-type thermoelectric elements are configured in arrays of linear active areas.

8. The integrated circuit of claim 1 , wherein the n-type thermoelectric elements and the p-type thermoelectric elements are configured in rectangular arrays of pillar active areas.

9. The integrated circuit of claim 1 , wherein the interconnects of the embedded thermoelectric device include interconnects of a first metal level of the integrated circuit, the interconnects of the first metal level making electrical and thermal connections to the stretch contacts, the interconnects of the first metal level overlapping the stretch contacts by an overlap distance which is 25 percent to 50 percent of an average pitch of the stretch contacts.

10. The integrated circuit of claim 1 , wherein the vias of the embedded thermoelectric device include stretch vias of a first via level of the integrated circuit, the stretch vias of the first via level making electrical and thermal connections to interconnects of a first metal level on the stretch contacts, the stretch vias of the first via level having lateral aspect ratios of greater than 4:1.

Assignees

• Texas Instruments Inc

Inventors

• Debord Jeffrey R
• Edwards Henry Litzmann
• Maggio Kenneth J

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/036

  the barrier, adhesion or liner layers being within a main fill metal · CPC title