Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9437607-B2
Application number	US-201313967492-A
Country	US
Kind code	B2
Filing date	Aug 15, 2013
Priority date	Sep 11, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A semiconductor device has a vertical channel and includes a first tunnel insulating layer adjacent to a blocking insulating layer, a third tunnel insulating layer adjacent to a channel pillar, and a second tunnel insulating layer between the first and third tunnel insulating layers. The energy band gap of the third tunnel insulating layer is smaller than that of the first tunnel insulating layer and is larger than that of the second tunnel insulating layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising:
alternately forming first material layers and second material layers on a substrate;
forming a hole through the second material layers and the first material layers and exposing the substrate;
forming a first tunnel insulation layer on an inner sidewall surface delimiting sides of the hole, forming a second tunnel insulating layer on the first tunnel insulating layer, and forming a third tunnel insulating layer on the second tunnel insulating layer such that the second tunnel insulating layer is located between the first and third tunnel insulating layers, and such that the nitrogen concentration of the third tunnel insulating layer is lower than that of the second tunnel insulating layer and higher than that of the first tunnel insulating layer; and
subsequently forming a semiconductor layer directly on the third tunnel insulation layer so as to be in contact with the third tunnel insulation layer,
wherein the forming the tunnel insulating layers comprises:
sequentially forming a first preliminary insulating layer, a second preliminary insulating layer, and a third preliminary insulating layer on the inner sidewall surface delimiting the sides of the hole, and
performing an oxidation treatment to convert the first preliminary insulating layer, the second preliminary insulating layer, and the third preliminary insulating layer to the first tunnel insulating layer, the second tunnel insulating layer, and the third tunnel insulating layer, respectively,
the first preliminary insulating layer includes at least one of a silicon oxide layer, a hafnium oxide layer, and an aluminum oxide layer,
wherein the second and third preliminary insulating layers each include at least one of a silicon oxynitride layer, a hafnium oxynitride layer, and an aluminum oxynitride layer, and
wherein a nitrogen concentration of the third preliminary insulating layer is higher than that of the second preliminary insulating layer.

2. The method of claim 1 , wherein the first, second, and third tunnel insulating layers include at least one of a silicon oxide layer, a hafnium oxide layer, and an aluminum oxide layer.

3. The method of claim 1 , further comprising:
selectively removing the first material layers to form recesses between the second material layers, and
forming gate electrodes in the recesses, respectively.

4. The method of claim 3 , further comprising:
forming a charge storage layer on the inner sidewall surface, that delimits the sides of the hole, before forming the first preliminary insulating layer.

5. The method of claim 4 , further comprising:
forming a blocking insulating layer in the recesses before forming the gate electrodes.

6. The method of claim 4 , further comprising:
forming a blocking insulating layer on the inner sidewall surface, that delimits the sides of the hole, before forming the charge storage layer.

7. The method of claim 3 , further comprising:
sequentially forming a charge storage layer and a blocking insulating layer in the recesses before forming the gate electrodes.

8. The method of claim 1 , wherein each of the first material layers comprises a silicon oxide layer, and
each of the second material layers comprises a conductive layer.

9. A method of manufacturing a semiconductor device, comprising:
alternately forming first material layers and second material layers on a substrate;
forming a hole through the second material layers and the first material layers and exposing the substrate;
forming a first tunnel insulating layer on an inner sidewall surface delimiting sides of the hole, forming a second tunnel insulating layer on the first tunnel insulating layer, and forming a third tunnel insulating layer on the second tunnel insulating layer such that the second tunnel insulating layer is located between the first and third tunnel insulating layers, and such that the nitrogen concentration of the third tunnel insulating layer is lower than that of the second tunnel insulating layer and higher than that of the first tunnel insulating layer; and
subsequently forming a semiconductor layer directly on the third tunnel insulating layer so as to be in contact with the third tunnel insulating layer,
wherein the forming the tunnel insulating layers comprises forming a first preliminary insulating layer on the inner sidewall surface delimiting the sides of the hole,
forming a second preliminary insulating layer on the first preliminary insulating layer,
forming a third preliminary insulating layer, having a nitrogen concentration higher than that of the second preliminary insulating layer, on the second preliminary insulating layer, and
performing a treatment that decreases the nitrogen concentration of the third preliminary insulating layer relative to that of the second preliminary insulating layer.

10. The method of claim 9 , wherein the treatment comprises thermally treating the structure constituted by the substrate and the preliminary insulating layers.

11. The method of claim 10 , wherein the treatment is performed under an oxidation atmosphere.

12. The method of claim 11 , wherein the oxidation atmosphere is an N 2 O gas atmosphere or an NO gas atmosphere.

13. The method of claim 10 , wherein the treatment is a radical oxidation process or a plasma oxidation process.

14. The method of claim 10 , wherein the treatment is performed at a temperature in a range of 750 degrees Celsius to 950 degrees Celsius.

15. The method of claim 9 , wherein the treatment comprises supplying oxygen into the second preliminary insulating layer, and supplying oxygen into the third preliminary insulating layer in an amount greater than that supplied into the second preliminary insulating layer.

Assignees

• Park Kwangmin
• Kim Byongju
• Yun Jumi
• Ahn Jaeyoung
• Samsung Electronics Co Ltd

Inventors

• Park Kwangmin
• Kim Byongju
• Yun Jumi
• Ahn Jaeyoung

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/6893 Primary

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic