Semiconductor device manufacturing method and semiconductor device

Patent metadata

Field	Value
Publication number	US-9437598-B2
Application number	US-201414528241-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Nov 7, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A semiconductor device manufacturing method includes: forming a first well of the first conductivity type in a substrate; forming a second well of the first conductivity type in a first region of the substrate; forming a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate; forming a fourth well, that surrounds the second well and has the second conductivity type, in the first region of the substrate; forming a fifth well of the first conductivity type above the first well in the second region of the substrate; and forming a sixth well of the second conductivity type above the first well in the second region of the substrate.

First claim

What is claimed is:

1. A semiconductor device manufacturing method comprising:
performing ion implantation of a first conductivity type to form a first well of the first conductivity type from a first depth of a substrate to a second depth greater than the first depth in the substrate;
performing ion implantation of the first conductivity type on a first region of the substrate to form a second well of the first conductivity type at a third depth from a surface of the substrate in the first region of the substrate;
performing ion implantation of a second conductivity type different from the first conductivity type on the first region of the substrate to form a third well of the second conductivity type underneath the second well in the first region of the substrate in a position overlapping with the first well located underneath the second well in the first region of the substrate;
performing ion implantation of the second conductivity type on the first region of the substrate to form a fourth well, that surrounds the second well in a plan view and has the second conductivity type, at a fourth depth from the surface of the substrate in the first region of the substrate;
performing ion implantation of the first conductivity type on a second region of the substrate to form a fifth well of the first conductivity type above the first well in the second region of the substrate; and
performing ion implantation of the second conductivity type on the second region of the substrate to form a sixth well of the second conductivity type above the first well in the second region of the substrate,
wherein:
the substrate includes a third region;
in the forming the third well, a seventh well of the second conductivity type is formed from a fifth depth of the substrate to a sixth depth greater than the fifth depth in the third region of the substrate by performing ion implantation of the second conductivity type;
the seventh well is located in a position overlapping with the first well in the third region of the substrate; and
in forming the fourth well, an eighth well of the second conductivity type is formed above the seventh well in the third region of the substrate by performing ion implantation of the second conductivity type in the third region of the substrate.

2. The semiconductor device manufacturing method according to claim 1 , wherein:
an outer edge of the third well is positioned outside the outer edge of the second well in a plan view; and
a bottom of the fourth well is positioned deeper than the bottom of the second well.

3. The semiconductor device manufacturing method according to claim 1 , further comprising:
forming a first gate insulating film on the substrate in the first region, a floating gate on the first gate insulating film, an intermediate insulating film on the floating gate, and a control gate on the intermediate insulating film; and
forming a second gate insulating film on the substrate in the second region, and a first gate electrode on the second gate insulating film.

4. The semiconductor device manufacturing method according to claim 1 , further comprising: forming a first gate insulating film on the substrate in the first region, a floating gate on the first gate insulating film, an intermediate insulating film on the floating gate, and a control gate on the intermediate insulating film; forming a second gate insulating film on the substrate in the second region, and a first gate electrode on the second gate insulating film; and forming a third gate insulating film on the substrate in the third region, and a second gate electrode shorter in gate length than the first gate electrode on the third gate insulating film.

5. The semiconductor device manufacturing method according to claim 1 , wherein the first conductivity type is a P type and the second conductivity type is an N type.

6. The semiconductor device manufacturing method according to claim 1 , wherein: in forming the second well, a ninth well of the first conductivity type is formed at the third depth from the surface of the substrate in the third region of the substrate by ion implantation of the first conductivity type on the third region of the substrate, within the substrate; the eighth well surrounds the ninth well in a plan view; and the seventh well is located underneath the eighth well and the ninth well.

7. A semiconductor device comprising:
a substrate that includes a first region and a second region;
a first well of a first conductivity type formed from a first depth to a second depth greater than the first depth of the substrate in the first region and the second region;
a second well of the first conductivity type formed at a third depth from a surface of the substrate in the first region;
a third well, that overlaps with the first well in the first region, of a second conductivity type different from the first conductivity type formed in the first region of the substrate and located underneath the second well;
a fourth well, that surrounds the second well in a plan view, of the second conductivity type formed at a fourth depth from the surface of the substrate in the first region;
a fifth well of the first conductivity type formed in the second region of the substrate and located above the first well in the second region; and
a sixth well of the second conductivity type formed in the second region of the substrate and located above the first well in the second region,
wherein the first well is formed in the third region of the substrate, the semiconductor device further comprising:
a seventh well of the second conductivity type formed from a fifth depth to a sixth depth greater than the fifth depth of the substrate in the third region;
the seventh well overlaps with the first well in the third region; and
an eighth well of the second conductivity type formed above the seventh well in the third region of the substrate.

8. The semiconductor device according to claim 7 , wherein:
an outer edge of the third well is positioned outside the outer edge of the second well in a plan view; and
a bottom of the fourth well is positioned deeper than the bottom of the second well.

9. The semiconductor device according to claim 7 , further comprising:
a first gate insulating film on the substrate in the first region;
a floating gate on the first gate insulating film;
an intermediate insulating film on the floating gate;
a control gate on the intermediate insulating film;
a second gate insulating film on the substrate in the second region; and
a first gate electrode on the second gate insulating film.

10. The semiconductor device according to claim 7 , further comprising; a first gate insulating film on the substrate in the first region; a floating gate on the first gate insulating film; an intermediate insulating film on the floating gate; a control gate on the intermediate insulating film; a second gate insulating film on the substrate in the second region; a first gate electrode on the second gate insulating film; a third gate insulating film on the substrate in the third region; and a second gate electrode shorter in gate length than the first gate electrode on the third gate insulating film.

11. The semiconductor device according to claim 7 , wherein the first conductivity type is a P type and the second conductivity type is an N type.

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Ogawa Hiroyuki
• Ariyoshi Junichi

Classifications

• H10D84/0156 Primary

  Manufacturing their doped wells · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/681 Primary

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H01L27/11531

  Electricity · mapped topic