Concentric bump design for the alignment in die stacking

Patent metadata

Field	Value
Publication number	US-9437551-B2
Application number	US-201414179854-A
Country	US
Kind code	B2
Filing date	Feb 13, 2014
Priority date	Feb 13, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
an alignment bump comprising:
a first non-solder metallic bump forming a ring encircling an opening therein, wherein the alignment bump is a dummy bump;

a dielectric layer having a top surface in contact with a bottom surface of the first non-solder metallic bump, wherein the dielectric layer extends directly underlying the opening; and
an active electrical connector comprising:
a second non-solder metallic bump, wherein a top surface of the first non-solder metallic bump and a top surface of the second non-solder metallic bump are substantially coplanar with each other, wherein the active electrical connector is electrically coupled to an active device.

2. The integrated circuit structure of claim 1 :
wherein the alignment bump further comprises:
a first solder layer overlapping and contacting the first non-solder metallic bump, wherein the first solder layer forms a ring encircling the opening therein; and

wherein the active electrical connector further comprises:
a second solder layer over and contacting the second non-solder metallic bump.

3. The integrated circuit structure of claim 1 further comprising a first package component, with the first package component comprising the alignment bump and the active electrical connector, and wherein the integrated circuit structure further comprises:
a second package component over the first package component; and
a solder region bonding the first non-solder metallic bump to the second package component.

4. The integrated circuit structure of claim 3 , wherein the solder region comprises:
a ring portion, with a void extending from a top surface of the first non-solder metallic bump up into the solder region; and
a top portion over the void, wherein the top portion is connected to the ring portion.

5. The integrated circuit structure of claim 3 , wherein a portion of the solder region that overlaps the opening has a bottom surface substantially level with a top surface of the first non-solder metallic bump.

6. The integrated circuit structure of claim 3 , wherein a portion of the solder region extends into the opening, and wherein a bottom surface of the solder region that is exposed to the opening has a rounded bottom surface.

7. The integrated circuit structure of claim 1 , wherein the alignment bump is cylindrical and is hollow inside.

8. An integrated circuit structure comprising:
a first package component comprising:
an alignment bump at a surface of the first package component, wherein the alignment bump is electrically floating, wherein the alignment bump forms a ring encircling an opening therein, and wherein the alignment bump comprises:
a first non-solder metallic bump;

a first electrical connector, wherein the first electrical connector has a solid shape with no opening therein, and wherein the first electrical connector comprises:
a second non-solder metallic bump;

a first solder region contacting the first non-solder metallic bump;
a second solder region contacting the second non-solder metallic bump; and
a second package component comprising:
a second electrical connector bonded to the first electrical connector through the first solder region; and
a metal bump bonded to the alignment bump through the second solder region.

9. The integrated circuit structure of claim 8 further comprising:
a first Post-Passivation Interconnect (PPI) pad in the first package component, wherein the first PPI pad is in contact with the first electrical connector; and
a second PPI pad in the first package component, wherein the second PPI pad is in contact with the alignment bump, and wherein the second PPI pad is electrically floating.

10. The integrated circuit structure of claim 8 , wherein the first package component further comprises two additional alignment bumps identical to the alignment bump, wherein the alignment bump and the two additional alignment bumps are distributed to three corners of the first package component.

11. The integrated circuit structure of claim 10 , wherein the alignment bump and the two additional alignment bumps are not aligned to any straight line.

12. The integrated circuit structure of claim 8 , wherein the alignment bump comprises an inner sidewall facing the opening, and an outer sidewall opposite to the inner sidewall, and wherein the inner sidewall and the outer sidewall are concentric.

13. The integrated circuit structure of claim 8 , wherein the opening extends into the second solder region.

14. The integrated circuit structure of claim 8 , wherein the first solder region comprises:
a ring portion, with a void extending from a top surface of the first non-solder metallic bump up into the first solder region; and
a top portion over the void, wherein the top portion is connected to the ring portion.

15. An integrated circuit structure comprising:
a device die comprising:
a first non-solder metallic bump forming a full ring, with an opening encircled by the full ring; and
a first solder region over the first non-solder metallic bump, wherein the first solder region contacts a top surface of the first non-solder metallic bump, and portions of the top surface of the first non-solder metallic bump in contact with the first solder region forms a full ring, and wherein the first solder region comprises:
a ring portion, with a void extending from a top surface of the first non-solder metallic bump up into the first solder region; and
a top portion over the void, wherein the top portion is connected to the ring portion.

16. The integrated circuit structure of claim 15 , wherein the first non-solder metallic bump is at a corner of the device die.

17. The integrated circuit structure of claim 15 , wherein the first solder region comprises a portion directly over and sealing the opening.

18. The integrated circuit structure of claim 15 further comprising a second non-solder metallic bump, with no opening encircled by the second non-solder metallic bump, wherein a top surface of the first non-solder metallic bump and a top surface of the second non-solder metallic bump are substantially coplanar with each other.

19. The integrated circuit structure of claim 15 , wherein the first non-solder metallic bump is not electrically coupled to any underlying conductive feature.

20. The integrated circuit structure of claim 15 further comprising a package component over and bonded to the device die, wherein the package component comprises a conductive feature bonded to the first non-solder metallic bump through the first solder region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Jung Wei
• Wang Tsung-Ding
• Lee Chien-Hsun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title