Integrated circuit package structure

Patent metadata

Field	Value
Publication number	US-9437512-B2
Application number	US-201213612764-A
Country	US
Kind code	B2
Filing date	Sep 12, 2012
Priority date	Oct 7, 2011
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip.

First claim

What is claimed is:

1. An integrated circuit (IC) package structure, comprising:
a first integrated circuit (IC) package, comprising:
a first sub-package, comprising:
a first package substrate, having opposite first and second surfaces;
a first semiconductor chip disposed over a first portion of the first surface of the first package substrate;
an encapsulant layer disposed over top and sidewall surfaces of the first semiconductor chip and the first portion of the first surface of the first package substrate; and
a plurality of first solder bumps disposed over the second surface of the first package substrate; and
a second sub-package stacked on top of the first sub-package, the second sub-package comprising:
a second package substrate, having opposite third and fourth surfaces;
a second semiconductor chip disposed over a portion of the third surface of the second package substrate, wherein the second semiconductor chip has a function different from that of the first semiconductor chip; and
a plurality of second solder bumps disposed between the fourth surface of the second package substrate and the first surface of the first package substrate;
a printed circuit board (PCB), having opposite fifth and sixth surfaces, wherein the first IC package is disposed over the fifth surface of the PCB and electrically connected to the first IC package via the plurality of first solder bumps;
a second IC package disposed over the fifth surface of the PCB; and
a plurality of bus lines formed in the fifth surface of the PCB electrically connecting the first semiconductor chip to the second IC package such that the first sub-package, the second sub-package, and the second IC package are configured in a side-by package on package (side-by POP) IC package structure;
wherein the first semiconductor chip is a microprocessor chip, and the second semiconductor chip is an integrated chip comprising a volatile memory device.

2. The IC package structure as claimed in claim 1 , wherein the second semiconductor chip comprises an LPDDR memory device.

3. The IC package structure as claimed in claim 1 , wherein the second IC package comprises a non-volatile memory device.

4. The IC package structure as claimed in claim 3 , wherein the non-volatile memory device comprises an eMMC™ memory device.

5. An integrated circuit (IC) package structure, comprising:
a printed circuit board (PCB);
a first integrated circuit (IC) package disposed over and electrically connected to the PCB, the first IC package comprising:
a first sub-package, comprising:
a first package substrate, having opposite first and second surfaces;
a first semiconductor chip disposed over a first portion of the first surface of the first package substrate;
an encapsulant layer disposed over top and sidewall surfaces of the first semiconductor chip and the first portion of the first surface of the first package substrate; and
a plurality of first solder bumps disposed over the second surface of the first package substrate; and
a second sub-package stacked on top of the first sub-package, the second sub-package comprising:
a second package substrate, having opposite third and fourth surfaces;
a second semiconductor chip disposed over a portion of the third surface of the second package substrate, wherein the second semiconductor chip has a function different from that of the first semiconductor chip; and
a plurality of second solder bumps disposed directly on the first surface of the first package substrate and outside the first portion of the first surface where the first semiconductor chip is disposed;
a second IC package disposed over the PCB; and
a plurality of bus lines formed in the PCB electrically connecting the first IC package to the second IC package such that the first sub-package, the second sub-package, and the second IC package are configured in a side-by package on package (side-by POP) IC package structure.

6. The IC package structure as claimed in claim 5 , wherein the first semiconductor chip is a microprocessor chip, and the second semiconductor chip is an integrated chip comprising a volatile memory device.

7. The IC package structure as claimed in claim 6 , wherein the second semiconductor chip comprises an LPDDR memory device.

8. The IC package structure as claimed in claim 5 , wherein the second IC package comprises a non-volatile memory device.

9. The IC package structure as claimed in claim 8 , wherein the non-volatile memory device comprises an eMMC™ memory device.

Assignees

• Gregorich Thomas Matthew
• Lin Tzu-Hung
• Mediatek Inc

Inventors

• Gregorich Thomas Matthew
• Lin Tzu-Hung

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title