Array substrate and fabrication method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9437487-B2
Application number	US-201414574721-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Nov 26, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer.

First claim

What is claimed is:

1. A fabrication method of an array substrate, the array substrate comprising gate lines and data lines intersecting with each other to define a plurality of pixel units, the method comprising:
forming a thin film transistor;
forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor;
forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode;
treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and
forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer,
wherein the via-hole conductive layer is provided at the via hole so that no portions of the via-hole conductive layer extent into a display region of each pixel unit.

2. The fabrication method of the array substrate according to claim 1 , further comprising: forming a common electrode, wherein the via-hole conductive layer and the common electrode are formed simultaneously, and the via-hole conductive layer and the common electrode are disconnected from each other.

3. The fabrication method of the array substrate according to claim 2 , further comprising:
forming an inter-electrode insulating layer on the via-hole conductive layer and the common electrode;
performing a patterning process on the inter-electrode insulating layer, so as to expose the via-hole conductive layer; and
treating the via-hole conductive layer, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode.

4. The fabrication method of the array substrate according to claim 3 , further comprising:
forming the pixel electrode on the inter-electrode insulating layer.

5. The fabrication method of the array substrate according to claim 1 , wherein the via-hole conductive layer is formed integrally with the pixel electrode.

6. The fabrication method of the array substrate according to claim 5 , further comprising:
forming a pixel electrode layer;
coating a photoresist on the pixel electrode layer, exposing and developing the photoresist by using a dual-tone mask to form a photoresist fully-reserved region, a photoresist partially-reserved region and a photoresist fully-removed region, the photoresist fully-reserved region corresponding to a region where the pixel electrode is to be formed, the photoresist partially-reserved region corresponding to a region where the via-hole conductive layer is to be formed, and the photoresist fully-removed region corresponding to other region;
removing the pixel electrode layer in the photoresist fully-removed region by etching;
removing the photoresist in the photoresist partially-reserved region by aching to form the via-hole conductive layer;
treating the via-hole conductive layer with remaining photoresist as a mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode; and
removing the remaining photoresist to obtain the pixel electrode.

7. The fabrication method of the array substrate according to claim 5 , further comprising:
forming a pixel electrode layer;
performing a patterning process on the pixel electrode layer by using a first single-tone mask to form the pixel electrode and the via-hole conductive layer; and
treating the via-hole conductive layer by using a second single-tone mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode.

8. The fabrication method of the array substrate according to claim 1 , wherein the treating the via-hole conductive layer comprises: treating the via-hole conductive layer by a hydrogen treatment process.

9. The fabrication method of the array substrate according to claim 8 , wherein hydrogen plasma is used in the hydrogen treatment process.

10. The fabrication method of the array substrate according to claim 1 , further comprising: forming a black matrix and a color filter layer, wherein the black matrix is formed to correspond to the thin film transistor, and the color filter layer is formed to correspond to the pixel electrode.

11. The fabrication method of the array substrate according to claim 1 , further comprising: forming an organic insulating layer, wherein the organic insulating layer is formed between a layer where the pixel electrode is provided and a layer where the drain electrode is provided.

12. The fabrication method of the array substrate according to claim 1 , further comprising: forming a spacer, wherein the spacer is provided in a topmost layer of the array substrate.

13. A fabrication method of an array substrate, comprising:
forming a thin film transistor;
forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor;
forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode;
treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and
forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer,
wherein the method further comprises:
forming a pixel electrode layer;
coating a photoresist on the pixel electrode layer, exposing and developing the photoresist by using a dual-tone mask to form a photoresist fully-reserved region, a photoresist partially-reserved region and a photoresist fully-removed region, the photoresist fully-reserved region corresponding to a region where the pixel electrode is to be formed, the photoresist partially-reserved region corresponding to a region where the via-hole conductive layer is to be formed, and the photoresist fully-removed region corresponding to other region;
removing the pixel electrode layer in the photoresist fully-removed region by etching;
removing the photoresist in the photoresist partially-reserved region by ashing to form the via-hole conductive layer;
treating the via-hole conductive layer with remaining photoresist as a mask, so that the reflectivity of the via-hole conductive layer is lower than the reflectivity of the drain electrode; and
removing the remaining photoresist to obtain the pixel electrode.

14. A fabrication method of an array substrate, comprising:
forming a thin film transistor;
forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor;
forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode;
treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and
forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer,
wherein the method further comprises:
forming a pixel electrode layer;
performing a patterning process on the pixel electrode layer by using a first single-tone mask to form the pixel electrod

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shu Shi
• Zhang Feng
• Gu Yaohui
• He Fang
• Gu Feng

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D30/6743

  Silicon · CPC title