Semiconductor line feature and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9437472-B2
Application number	US-201414192439-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Feb 27, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.

First claim

What is claimed is:

1. A manufacturing method for a semiconductor isolation structure, comprising:
patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a substrate by performing a first plasma etch at a first temperature;
forming a trench having a sidewall angle greater than 88 degrees in the substrate correlated to the line feature by performing a second plasma etch at a second temperature;
rounding a bottom of the trench by performing a thi…

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fang Wen-Han
• Wu Po-Chi

Classifications

• H10P50/694

  Electricity · mapped topic

• H10P50/692

  Electricity · mapped topic

• H10P50/283

  Electricity · mapped topic

• H10P50/242

  Electricity · mapped topic

• H10W10/0145 Primary

  Electricity · mapped topic