Electronic device

US9437289B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9437289-B2
Application numberUS-201414219381-A
CountryUS
Kind codeB2
Filing dateMar 19, 2014
Priority dateAug 14, 2013
Publication dateSep 6, 2016
Grant dateSep 6, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising a semiconductor memory unit which comprises: a plurality of storage cells each comprising a variable resistance element of which resistance value changes with a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines, each coupled to a selecting element of a corresponding storage cell of the plurality of storage cells; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells in accordance with a temperature change; an access control unit electrically coupled to the first and second lines and providing a write current or a read current to a selected storage cell among the plurality of storage cells; and a word line control unit configured to adjust an activation voltage level applied to the selected word line in accordance with a temperature change, wherein when the decrease in resistance of the variable resistance element according to the increase of temperature is smaller than the sum of the increase in resistance of the selecting element according to the increase of temperature, the increase in resistance of the first line according to the increase of temperature, and the increase in resistance of the second line according to the increase of temperature, the write current and the read current decrease with the increase of temperature. 2. The electronic device of claim 1 , wherein when the temperature increases, a switching current corresponding to a minimum current to change a state of the variable resistance element decreases, a resistance value of the variable resistance element decreases, resistance values of the selecting element, the first and second lines increase. 3. The electronic device of claim 1 , wherein the voltage adjuster increases the back bias voltage level when the temperature increases during a write operation in case where the decrease of the switching current according to the increase of temperature is smaller than the decrease of the write current according to the increase of temperature, increases the back bias voltage level when the temperature decreases during the write operation in case where the decrease of the switching current according to the increase of temperature is larger than the decrease of the write current according to the decrease of temperature, and maintains the back bias voltage level at a set voltage level during the write operation in case where the decrease of the switching current according to the increase of temperature is equal to the decrease of the write current according to the increase of temperature. 4. The electronic device according to claim 3 , wherein the word line control unit increases the activation voltage level when the temperature increases during a write operation in case where a decrease of the switching current according to the increase of temperature is smaller than a decrease of the write current according to the increase of temperature, decreases the activation voltage level when the temperature increase during the write operation in case where the decrease of the switching current according to the increase of temperature is larger than the decrease of the write current according to the decrease of temperature, and maintains the activation voltage level at a set voltage level during the write operation in case where the decrease of the switching current according to the increase of temperature is equal to the decrease of the write current according to the increase of temperature. 5. The electronic device according to claim 4 , wherein the voltage adjuster increases the back bias voltage level when the temperature increases during a read operation, and wherein the word line control unit increases the activation voltage level when the temperature increases during a read operation. 6. The electronic device according to claim 1 , further comprising a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the variable resistance element is part of the cache memory unit in the processor. 7. The electronic device according to claim 1 , further comprising a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the variable resistance element is part of the storage device or the temporary storage device in the data storage system. 8. The electronic device according to claim 1 , wherein when the decrease in resistance of the variable resistance element according to the increase of temperature is larger than the sum of the increase in resistance of the selecting element according to the increase of temperature, the increase in resistance of the first line according to the increase of temperature, and the increase in resistance of the second line according to the increase of temperature, the write current and the read current increase with the increase of temperature, wherein the voltage adjuster increases the back bias voltage level with the decrease of temperature, wherein the word line control unit increases the activation voltage level with the decrease of temperature. 9. The electronic device according to claim 1 , wherein when the decrease in resistance of the variable resistance element according to the increase of temperature is equal to the sum of the increase in resistance of the selecting element according to the increase of temperature, the increase in resistance of the first line according to the increase of temperature, and the increase in resistance of the second line according to the increase of temperature, the write current and the read current are maintained at set values, wherein the voltage adjuster increases the back bias voltage level when the temperature decreases during a write operation, and maintains the back bias voltage level at a set voltage level during a read operation, wherein the word line control unit increases the activation voltage level when the temperature decreases during a write operation, and maintains the activation voltage level at a set voltage level during a read operation. 10. An electronic device comprising a semiconductor memory unit which comprises: a first global line; a second global line; a plurality of cell arrays each including a plurality of storage cells including a selecting element, a variable resistance element of which resistance changes based on a current flowing across the variable resistance element, a first line coupled to on

Assignees

Inventors

Classifications

  • Power supply circuits · CPC title

  • using resistive RAM [RRAM] elements · CPC title

  • with means for avoiding disturbances due to temperature effects · CPC title

  • Bit-line or column circuits · CPC title

  • Array wherein each memory cell has more than one access device · CPC title

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What does patent US9437289B2 cover?
Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corres…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification G11C13/003. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).