Methods, devices and processes for multi-state phase change devices

Patent metadata

Field	Value
Publication number	US-9437287-B2
Application number	US-201514975410-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Aug 7, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be programmed to transition among more than two states representing multiple bits of information. Methods for manufacture and use are also disclosed.

First claim

We claim:

1. A method of operating a phase change device, comprising applying an electrical signal across parallel first and second phase change materials resulting, at least in part, in a change of resistive state of at least one of the first and second phase change materials, wherein a crystalline state resistance of the second phase change material is larger than a crystalline state resistance of the first phase change material to permit differentiation among resistive states.

2. The method of claim 1 , wherein applying the electrical signal comprises operating the at least one of the first and second phase change materials as a self-heater to cause the change of resistive state.

3. The method of claim 1 , further comprising:
detecting a resistance exhibited by a combination of the first and second phase change materials; and
determining a logical state depending upon the resistance exhibited by a combination of the first and second phase change materials.

4. The method of claim 1 , wherein applying the electrical signal comprises:
changing a resistive state of the first phase change material without changing a resistive state of the second phase change material.

5. The method of claim 1 , wherein applying the electrical signal comprises changing resistive states of the first and second phase change materials.

6. The method of claim 1 , wherein applying the electrical signal comprises changing a logic state of a memory cell including both the first and second phase change materials from a first resistive state to a second resistive state, further comprising, subsequent to applying the electrical signal, applying a second electrical signal across the first and second phase change materials to change the logic state of the memory cell from the second resistive state to a third resistive state.

7. The method of claim 1 , wherein the first and second resistive states differ in resistance differ by a factor of at least two.

8. The method of claim 1 , wherein applying the electrical signal further comprises applying the electrical signal across a third phase change material connected in parallel with the first and second phase change materials.

9. The method of claim 8 , further comprising:
detecting a resistance exhibited by a combination of the first, second, and third phase change materials; and
determining a logical state depending upon the resistance exhibited by a combination of the first, second and third phase change materials.

10. A method of programming a resistive memory device, comprising:
providing a resistive memory cell comprising a first resistance change material and a second resistance change material electrically connected in parallel between a common first electrode and a common second electrode; and
switching the resistive memory cell between a first logic state and a second logic state by applying a bias between the common first and second electrodes to cause at least one of the first and second resistance change materials to undergo a change in resistance state.

11. The method of claim 10 , wherein each of the first resistance change material and the second resistance change material is configured to threshold in response to a bias exceeding a respective threshold voltage.

12. The method of claim 10 , wherein each of the first and second resistance change materials is configured undergo a change in resistance state from a respective RESET state to a respective SET state in response to a respective SET voltage, and further configured to undergo a change in resistance state from a respective SET state to a respective RESET state in response to a respective RESET voltage.

13. The method of claim 12 , wherein switching comprises switching the resistive memory cell to the first logic state by causing first and second resistance change materials to undergo changes in resistance states from the respective RESET states to the respective SET states by applying a greater of the respective SET voltages as the bias, or comprises switching the resistive memory cell to the second logic state by causing first and second resistance change materials to undergo changes in resistance states from the respective SET states to the respective RESET states by applying a greater of the respective RESET voltages as the bias.

14. The method of claim 12 , further comprising switching to a third logic state or a fourth logic state by causing the first resistance change material to undergo a change in resistance state without causing the second resistance change material undergo a change in resistance state.

15. The method of claim 14 , wherein additionally switching comprises switching to the third logic state by causing only one of the first and second resistance change materials to undergo a change in resistance from the respective SET states to a respective RESET state by applying a lower of the respective RESET voltages as the bias.

16. The method of claim 14 , wherein additionally switching comprises switching to the fourth logic state by causing only one of the first and second resistance change materials to undergo a change in resistance from the respective RESET states to the respective SET state by applying a lower of the respective SET voltages as the bias.

17. The method of claim 10 , wherein the first resistance change material comprises a first phase change material composition and the second resistance change material comprises a second phase change material composition different from the first phase change material composition.

18. The method of claim 17 , wherein switching comprises causing the at least one of the first and second resistance change materials to undergo a change in resistance comprises causing a phase change.

19. The method of claim 18 , wherein switching causing the change in resistance comprises self-heating the at least one of the first and second resistance change material to cause the phase change.

Assignees

• Micron Technology Inc

Inventors

• Colombo Davide
• Erbetta Davide

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/5678 Primary

  using amorphous/crystalline phase transition storage elements · CPC title

• Y10T428/24942

  including components having same physical characteristic in differing degree · CPC title

• B32B7/02

  Physical, chemical or physicochemical properties · CPC title