Multi-core page table sets of attribute fields

US9436616B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9436616-B2
Application numberUS-201313888069-A
CountryUS
Kind codeB2
Filing dateMay 6, 2013
Priority dateMay 6, 2013
Publication dateSep 6, 2016
Grant dateSep 6, 2016

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of accessing memory comprising: reading, with a first processing unit, a physical address from a first page table entry in a first page table; determining, with the first processing unit, first page attribute data from the first page table entry, wherein the first page attribute data define one or more accessibility attributes of the physical page of memory for the first processing unit, and wherein the first page attribute data is included in one or more first fields; reading, with a second processing unit, the physical address from the first page table entry in the first page table; determining, with the second processing unit, second page attribute data from an alternative location, wherein the alternate location includes one or more second fields that are separate from the one of more first fields, the alternate location is a page table entry that is separate from the first page table entry, the alternative location is associated with the first page table entry, and wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit; accessing, with the first processing unit, a physical page of memory associated with the physical address according to the one or more accessibility attributes of the first page attribute data; and accessing, with the second processing unit, the physical page of memory associated with the physical address according to the one or more accessibility attributes of the second page attribute data. 2. The method of claim 1 , wherein the alternative location comprises a second page table entry in a second page table, wherein determining the second page attribute data further comprises: determining, with the second processing unit, the second page attribute data from the second page table entry in parallel with reading the first page table entry. 3. The method of claim 1 , wherein the alternative location is a second page table entry in a second page table, the method further comprising: reading, with the second processing unit, data associated with the second page table from the first page table entry, wherein determining the second page attribute data further comprises: identifying, with the second processing unit, the second page table based on the data associated with the second page table. 4. The method of claim 3 , wherein the data associated with the second page table comprises an identifier that identifies the second page table from a plurality of parallel page tables. 5. The method of claim 1 , wherein the alternative location comprises a second page table entry in the first page table, wherein the second page table entry in the first page table is associated with the first page table entry based on a pointer value of the first page table entry. 6. The method of claim 5 , wherein the pointer value comprises at least one of a virtual address and a physical address. 7. The method of claim 1 , further comprising: combining, with the second processing unit, the one or more attributes of the first page attribute data with one or more attributes of the second page attribute data to form one or more accessibility attributes of combined page attribute data, wherein the second processing unit accesses the physical page of memory associated with the physical address according to the one or more attributes of the combined page attribute data. 8. The method of claim 7 , wherein the second page attribute data includes one or more attribute values that are different from the one or more attribute values of the first page attribute data. 9. The method of claim 1 , further comprising: reading, with the first processing unit, valid data from the first page table entry that indicates whether the second page attribute data is valid, wherein determining the second page attribute data further comprises: determining, with the second processing unit, the second page attribute data if the valid data from the first page table entry indicates that the second page attribute data is valid. 10. The method of claim 1 , wherein the first page attribute data and the second page attribute data define whether the page of memory is at least one of: readable, writeable, cacheable, executable, and dirty. 11. The method of claim 1 , wherein the alternative location comprises a register, wherein the register is associated with the first page table entry based on a pointer value in the first page table entry. 12. The method of claim 1 , wherein the first processing unit is a CPU, and the second processing unit is a GPU. 13. The method of claim 12 wherein the first processing unit comprises a first memory management unit (MMU) and the second processing unit comprises a second MMU, wherein the first MMU is configured to access at least one of the first page table and the alternate location, and the second MMU is configured to access at least one of the first page table and the alternate location. 14. An apparatus comprising: means for storing: a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address; an alternative location associated with the first page table entry; and a physical page of memory associated with the physical address; first means for processing, wherein the first means for processing comprises: means for reading, from the first page table entry, the physical address; means for determining first page attribute data from the first page table entry, wherein the first page attribute data define one or more accessibility attributes of the physical page of memory for the first means for processing, and wherein the first page attribute data is included in one or more first fields; and means for accessing a physical page of memory with the physical address according to the one or more accessibility attributes of the first page attribute data; a second means for processing, wherein the second means for processing comprises: means for reading, from the first page table, the first page table entry; means for determining the physical address from the first page table entry; means for determining second page attribute data from the alternative location, wherein the alternate location includes one or more second fields that are separate from the one of more first fields, the alternate location is a page table entry that is separate from the first page table entry, the alternative location is associated with the first page table entry, and wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second means for processing; and means for accessing the physical page of memory associated with the physical address according to the one or more accessibility attributes of the second page attribute data. 15. The apparatus of claim 14 , wherein the alternative location comprises a second page table entry in a second page table, wherein the means for determining the second page attribute data further comprises: means for determining the second page attribute data from the second page table entry in parallel with the means for determining the first page attribute data. 16. The apparatus of claim 14 , wherein the alternative location is a second page table entry in a second page table, the second means for processing further comprising: means for reading data associated with the second page table from the first page table entry, wherein the means for determining the second page attribute data further comprises: means f

Assignees

Inventors

Classifications

  • the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

  • using page tables, e.g. page table structures · CPC title

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What does patent US9436616B2 cover?
A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the phys…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/1009. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).