Optimistic data read

Patent metadata

Field	Value
Publication number	US-9436615-B2
Application number	US-201414506124-A
Country	US
Kind code	B2
Filing date	Oct 3, 2014
Priority date	Oct 3, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A storage module may include a controller that is configured to perform a read operation to read data stored in at least one memory, where the data is associated with logical address information. In order to perform the read operation, the controller may be configured to retrieve a preliminary physical address associated with the logical address information, and initiate a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information.

First claim

I claim:

1. A storage system comprising:
at least one memory; and
control circuitry in communication with the at least one memory, wherein the control circuitry, in order to perform a read operation to read data stored in the at least one memory, is configured to:
identify logical address information associated with the data;
retrieve a first physical address associated with the logical address information from a first address data structure of a plurality of address data structures;
initiate a data retrieval process of the read operation for a first version of the data stored at the first physical address;
retrieve a second physical address associated with the logical address from a second data structure of the plurality of address data structure;
when the second physical address matches the first physical address, complete the read operation using the first version of the data; and
when the second physical address does not match the first physical address, terminate the initiated data retrieval process and initiate a subsequent data retrieval process for a second version of the data stored at the final physical address.

2. The storage system of claim 1 , wherein the first address data structure comprises a primary address data structure.

3. The storage system of claim 1 , wherein the plurality of address data structures comprises a primary address data structure and a plurality of secondary address data structures, wherein the first address data structure comprises the primary address data structure or a first secondary address data structure of the plurality secondary address data structure, and wherein the second address data structure a second secondary address data structure of the plurality of secondary address data structures.

4. The storage system of claim 1 , wherein the first physical address comprises a first preliminary physical address, and wherein the control circuitry is further configured to:
determine that the second physical address matches the first preliminary address when the query of the second address data structure returns either mapping information identifying that the second address data structure does not have a logical-physical address mapping associated with the logical address information or a second preliminary physical address that matches the first preliminary physical address; and
determine that the second physical address does not match the first preliminary physical address when the query of the second address data structure returns the second preliminary physical address and the second preliminary physical address does not match the first preliminary physical address.

5. The storage system of claim 1 , wherein the at least one memory comprises a first memory and a second memory, the first memory configured with a higher bit-per-cell storage density than the second memory,
wherein the first address data structure provides logical-physical address mapping for the first memory, and
wherein the second address data structure provides logical-physical address mapping for the second memory.

6. The storage system of claim 1 , wherein the second address data structure tracks changes to entries in the first address data structure.

7. The storage system of claim 1 , wherein the at least one memory comprises a local memory that is internal to the controller, and wherein the second address data structure identifies whether a most recent version of the data is stored in the local memory.

8. The storage system of claim 1 , wherein the control circuitry is further configured to:
communicate with the at least one memory using a plurality of different channels;
retrieve the second address data structure before initiating the data retrieval process when the control circuitry uses a same channel of the plurality of different channels to retrieve the second address data structure and initiate the data retrieval process.

9. The storage system of claim 1 , wherein the control circuitry is further configured to:
concurrently initiate the data retrieval process using a first channel and retrieve the second address data structure using a second channel.

10. The storage system of claim 1 , wherein the control circuitry is further configured to receive, from a host system, a host read request identifying the logical address information,
wherein when the second physical address matches the first physical address, the control circuitry is further configured to send the first version of the data to the host system to complete the read operation.

11. The storage system of claim 1 , wherein the read operation comprises a background read operation, wherein the control circuitry is further configured to: identify the logical address information as part of the background read operation, and send the data to a new location in the at least one memory to complete the background read operation.

12. The storage system of claim 1 , wherein one or more of the at least one memory comprises three-dimensional memory.

13. The storage system of claim 1 , wherein the control circuitry is on the same substrate as memory elements of the at least one memory.

14. The storage system of claim 1 , wherein the control circuitry is further configured to confirm a final physical address associates with the logical address information based on the retrieval of the second physical address from the second data structure.

15. The storage system of claim 14 , wherein the control circuitry is further configured to send to the at least one memory one or more sense commands that instruct the at least one memory to sense the first version of the data stored at the first physical address before confirming the final physical address.

16. The storage system of claim 14 , wherein the control circuitry is further configured to:
confirm the final physical address prior to completion of the data retrieval process for the first version of the data at the first physical address.

17. The storage system of claim 14 , wherein the control circuitry is further configured to:
complete the data retrieval process for the first version of the data at the first physical address prior to confirmation of the final physical address.

18. A method of accelerating a logical-to-physical address translation, the method comprising:
performing in a storage system having at least one memory:
receiving, from a host system, a host request identifying logical address information for data stored in the at least one memory;
reading a preliminary physical address associated with the logical address information from a first data structure of a plurality of address data structures;
initiating a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information;
while continuing with the data retrieval process, querying a second address data structure of the plurality of address data structures to confirm the final physical address, the second address data structure different from the first address data structure; and
when the final physical address does not match the preliminary physical address, terminating the initiated data retrieval process and initiating a subsequent data retrieval process for a second version of the data stored at the final physical address.

19. The method of claim 18 , wherein the first address data structure comprises a primary address data structure, and the second address data structure comprises a secondary address data stru

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Gorobets Sergey Anatolievich

Classifications

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/10 Primary

  Address translation · CPC title