Method and apparatus for per core performance states

Patent metadata

Field	Value
Publication number	US-9436254-B2
Application number	US-201213976682-A
Country	US
Kind code	B2
Filing date	Mar 13, 2012
Priority date	Mar 13, 2012
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores, wherein each core comprises logic to:
receive a performance state request from each of one or more threads;
resolve the performance state request from each of the one or more threads to determine a resolved performance state request; and
indicate the resolved performance state request to a power control module; and

the power control module coupled to the plurality of cores, wherein the power control module is to facilitate each core to operate at a different performance state from the other cores based at least in part on the resolved performance state from each of the plurality of cores.

2. The processor of claim 1 , wherein the power control module is to:
facilitate each core to operate at a voltage level and a frequency setting that are different from the other cores.

3. The processor of claim 1 , wherein the power control module is further to:
determine the resolved performance state request from each core;
send a multi-cast message to all cores having a common resolved performance state to switch to the common resolved performance state; and
send an uni-cast message to each core having a different resolved performance state from the common resolved performance state to switch to the different resolved performance state.

4. The processor of claim 1 , wherein each core comprises a register, and wherein the logic in each core is to set one or more bits of the register to indicate the resolved performance state request to the power control module.

5. The processor of claim 1 , wherein the logic is to:
determine a first maximum performance state of the one or more threads;
determine a second maximum performance state from the performance state request from each of the one or more threads;
determine whether the second maximum performance state is higher than the first maximum performance state; and
determine the resolved performance state request based on the second maximum performance state in response to a determination that the second maximum performance state is different from the first maximum performance state.

6. The processor of claim 1 , wherein the performance state request from each of one or more threads comprises a sleep state request, and wherein the logic is to:
suppress the sleep state request from each of the one or more threads when a duration of the sleep state request is less than a duration of a core switch to the sleep state.

7. The processor of claim 1 , wherein the performance state request from each of one or more threads comprises a transient sleep state request, and wherein the logic is to:
retain a voting right for each thread having the transient sleep state request.

8. The processor of claim 1 , wherein the performance state request from each of one or more threads comprises a wake request, and wherein the logic is to:
determine a prior performance state of each thread having the wake request, wherein the prior performance state is a performance state of each thread prior to entry into a sleep state; and
determine the resolved performance state request based on the prior performance state of each thread having the wake request.

9. The processor of claim 1 , wherein the power control module is further to:
determine that all resolved performance state requests from each core are sleep state requests; and
indicate that the processor is in a sleep state.

10. A system comprising:
a memory;
a processor coupled with the memory, the processor comprising:
a plurality of cores, wherein each core comprises logic to:
receive a performance state request from each of one or more threads;
resolve the performance state request from each of the one or more threads to determine a resolved performance state request; and
indicate the resolved performance state request to a power control module; and

the power control module coupled to the plurality of cores, wherein the power control module is to facilitate each core to operate at an independent performance state based at least in part on the resolved performance state from each of the plurality of cores.

11. The system of claim 10 , wherein the power control module is to:
facilitate each core to operate at an independent voltage level and an independent frequency setting such that thermal and electrical constraints of the system are not violated.

12. The system of claim 10 , wherein the power control module is further to:
determine the resolved performance state request from each core;
send a multi-cast message to all cores having a common resolved performance state to switch to the common resolved performance state; and
send an uni-cast message to each core having a different resolved performance state from the common resolved performance state to switch to the different resolved performance state.

13. The system of claim 10 , wherein each core comprises a register, and wherein the logic in each core is to set one or more bits of the register to indicate the resolved performance state request to the power control module.

14. The system of claim 10 , wherein the logic in each core is to:
determine a first maximum performance state of the one or more threads;
determine a second maximum performance state from the performance state request from each of the one or more threads;
determine whether the second maximum performance state is different than the first maximum performance state; and
determine the resolved performance state request based on the second maximum performance state in response to a determination that the second maximum performance state is different from the first maximum performance state.

15. The system of claim 10 , wherein the performance state request from each of one or more threads comprises a sleep state request, and wherein the logic is to:
suppress the sleep state request from each of the one or more threads when a duration of the sleep state request is less than a duration of a core switch to the sleep state.

16. The system of claim 10 , wherein the performance state request from each of one or more threads comprises a transient sleep state request, and wherein the logic is to:
retain a voting right for each thread having the transient sleep state request.

17. The system of claim 10 , wherein the performance state request from each of one or more threads comprises a wake request, and wherein the logic is to:
determine a prior performance state of each thread having the wake request, wherein the prior performance state is a performance state of each thread prior to entering a sleep state; and
determine the resolved performance state request based on the prior performance state of each thread having the wake request.

18. The system of claim 10 , wherein the power control module is further to:
determine that all resolved performance state requests from each core are sleep state requests; and
indicate that the processor is in a sleep state.

19. A method comprising:
receiving, in a logic of a core of a multicore processor, a performance state request from each of one or more threads;
resolving, in the logic, the performance state request from each of the one or more threads to determine a resolved performance state request; and
indicating, from the core, the resolved performance state request to a performance control module of the multicore processor.

20. The method of claim 19 , wherein indicating the resolved performance state request to the performance control module comprises setting one or

Assignees

• Bhandaru Malini K
• Dehaemer Eric J
• Ho Samuel W
• Bobholz Scott P
• Poirier Chris
• Intel Corp

Inventors

• Bhandaru Malini K
• Dehaemer Eric J
• Ho Samuel W
• Bobholz Scott P
• Poirier Chris

Classifications

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/329

  by task scheduling · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• Y02B60/1239

  Cross-Sectional Technologies · mapped topic

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title