Integrated circuit device and method therefor

Patent metadata

Field	Value
Publication number	US-9435862-B2
Application number	US-201414330544-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Jul 14, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

An integrated circuit device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device. The at least one clock control component is further arranged to receive at least one indication of at least one power dissipation parameter for at least a part of the IC device, and modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device.

First claim

The invention claimed is:

1. An integrated circuit, IC, device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device; wherein the at least one clock control component is further arranged to:
receive at least one indication of at least one power dissipation parameter for at least a part of the IC device; and
modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device,
wherein the at least one indication of at least one power dissipation parameter comprises at least one static power dissipation parameter value, and the at least one static power dissipation parameter value is/are configured within at least one register accessible by the at least one clock control component.

2. The IC device of claim 1 , wherein the at least one register is configurable by at least one external device operably coupled to the IC device to enable the at least one external device to load the at least one static power dissipation parameter value into the at least one register.

3. The IC device of claim 2 , wherein the IC device further comprises at least one memory element comprising non-volatile memory within which the at least one static power dissipation parameter value is arranged to be pre-configured and from which the at least one static power dissipation parameter value is arranged to be loaded into the at least one register.

4. The IC device of claim 1 , wherein the IC device further comprises at least one memory element comprising non-volatile memory within which the at least one static power dissipation parameter value is arranged to be pre-configured and from which the at least one static power dissipation parameter value is arranged to be loaded into the at least one register.

5. The IC device of claim 1 , wherein the at least one indication of at least one power dissipation parameter comprises at least one dynamic power dissipation parameter value.

6. The IC device of claim 5 , wherein the at least one dynamic power dissipation parameter value comprises at least one from a group comprising at least one of:
at least one sensor measurement indication; and
at least one IC device activity indication.

7. The IC device of claim 6 , wherein the at least one clock control component comprises at least one mapping component arranged to perform mapping of the at least one received dynamic power dissipation parameter value to derive at least one clock configuration parameter, and the at least one clock control component is arranged to modulate the at least one clock signal provided to the at least one self-test component based at least partly on the derived at least one clock configuration parameter.

8. The IC device of claim 5 , wherein the at least one clock control component comprises at least one mapping component arranged to perform mapping of the at least one received dynamic power dissipation parameter value to derive at least one clock configuration parameter, and the at least one clock control component is arranged to modulate the at least one clock signal provided to the at least one self-test component based at least partly on the derived at least one clock configuration parameter.

9. The IC device of claim 8 , wherein the at least one mapping component comprises at least one mapping circuit arranged to perform at least a part of the mapping of the at least one received dynamic power dissipation parameter value to derive at least one clock configuration parameter.

10. The IC device of claim 9 , wherein the at least one clock control component is arranged to perform at least a part of the mapping of the at least one received sensor measurement indication based at least partly on a lookup table stored within an area of memory of the IC device.

11. The IC device of claim 8 , wherein the at least one clock control component is arranged to perform at least a part of the mapping of the at least one received sensor measurement indication based at least partly on a lookup table stored within an area of memory of the IC device.

12. The IC device of claim 1 , wherein the at least one indication of at least one power dissipation parameter for at least a part of the IC device comprises at least one from a group comprising at least one of:
at least one static power dissipation parameter value derived from at least one of:
at least one process characteristic of the IC device;
at least one package characteristic of the IC device; and
at least one temperature range specification characteristic of the IC device; and
at least one dynamic power dissipation parameter value comprising at least one of:
at least one temperature measurement;
at least one current measurement for at least one current within the IC device;
at least one supply voltage level indication for at least a part of the IC device; and
at least one activity indication for at least a part of the IC device.

13. A method of generating at least one clock signal for at least one self-test component within an integrated circuit, IC, device, the method comprising:
receiving at least one indication of at least one power dissipation parameter for at least a part of the IC device; and
modulating at least one clock signal to generate the at least one clock signal for the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device, wherein the at least one indication of at least one power dissipation parameter comprises at least one static power dissipation parameter value, and the at least one static power dissipation parameter value is/are configured within at least one register accessible by at least one clock control component.

Assignees

• Litovchenko Vladimir
• Ahrens Heiko
• Stahl Andreas Roland
• Freescale Semiconductor Inc

Inventors

• Litovchenko Vladimir
• Ahrens Heiko
• Stahl Andreas Roland

Classifications

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/3187 Primary

  Built-in tests · CPC title