Soldering method and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9434028-B2
Application number	US-201414301425-A
Country	US
Kind code	B2
Filing date	Jun 11, 2014
Priority date	Jun 25, 2013
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Provided is a soldering method through nickel plating layer to reduce void occurrence rate and a method of manufacturing semiconductor device by using the soldering method. By heating a copper base plate having a nickel plating layer at a temperature range of 300° C. to 400° C. in an inert gas atmosphere beforehand, void occurrence rate can be reduced in soldering the copper base plate to an insulating circuit board.

First claim

What is claimed is:

1. A soldering method comprising:
heat treating a member having a nickel plating layer including hydrogen in a heat treating temperature range of 300° C. to 400° C. in an inert gas atmosphere, thereby reducing a nickel oxide film on a surface of the nickel plating layer;
disposing a solder between the heat-treated member and a joined member; and
joining the heat-treated member to the joined member with the solder in a reducing gas atmosphere at a second temperature lower than the heat treating temperature.

2. The soldering method according to claim 1 , wherein the nickel plating layer is formed by electroless plating treatment.

3. The soldering method according to claim 1 , wherein the heat treating temperature range is 320° C. to 360° C.

4. The soldering method according to claim 1 , wherein the inert gas is nitrogen gas or argon gas.

5. The soldering method according to claim 1 , wherein the second temperature is in a temperature range of 200° C. to 300° C.

6. A method of manufacturing a semiconductor device comprising:
heat treating a base plate having a nickel plating layer including hydrogen in a heat treating temperature range of 300° C. to 400° C. in an inert gas atmosphere, thereby reducing a nickel oxide film on a surface of the nickel plating layer;
disposing a solder between the heat-treated base plate and an insulating circuit board; and
joining the heat-treated base plate to a conductive foil of the insulating circuit board with the solder in a reducing gas atmosphere at a second temperature lower than the heat treating temperature.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein the nickel plating layer is formed by electroless plating treatment.

8. The method of manufacturing a semiconductor device according to claim 6 , wherein the heat treating temperature range is 320° C. to 360° C.

9. The method of manufacturing a semiconductor device according to claim 6 , wherein the conductive foil has a nickel plating layer.

10. The method of manufacturing a semiconductor device according to claim 6 , wherein the inert gas is nitrogen gas or argon gas.

11. The method of manufacturing a semiconductor device according to claim 6 , wherein the base plate comprises copper, aluminum, AISiC, or MgSiC.

12. The method of manufacturing a semiconductor device according to claim 6 , wherein the insulating circuit board comprises a ceramic plate with conductive foils disposed on both sides of the ceramic plate.

13. The method of manufacturing a semiconductor device according to claim 6 , wherein the conductive foil is a copper foil.

14. The method of manufacturing a semiconductor device according to claim 6 , wherein the second temperature is in a temperature range of 200° C. to 300° C.

Assignees

• Fuji Electric Co Ltd

Inventors

• Iso Akira

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W76/157

  having interconnections parallel to the insulating or insulated base · CPC title

• H10W72/07554

  changes in dispositions · CPC title