Silicon-on-nothing finfets
US-2015076561-A1 · Mar 19, 2015 · US
Substrate via filling
US9433101B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9433101-B2 |
| Application number | US-201414515567-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 16, 2014 |
| Priority date | Oct 16, 2014 |
| Publication date | Aug 30, 2016 |
| Grant date | Aug 30, 2016 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for filling vias on a substrate with metal, the method comprising: receiving a substrate comprising a plurality of vias; bonding a metal plating layer onto a first side of the substrate; etching the vias to remove a bonding adhesive from the metal plating layer within the vias and thereby prepare the vias for fill-plating; fill-plating the vias with a first metal to provide a filled substrate; and removing at least a portion of the metal plating layer from the filled substrate to provide a finished substrate.
Assignees
Inventors
Classifications
characterised by the relative positions of pads or connectors relative to package parts · CPC title
Ceramics or glasses · CPC title
Through-vias · CPC title
for connecting multiple chips together · CPC title
of vias therein · CPC title
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Frequently asked questions
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- What does patent US9433101B2 cover?
- A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently pattern…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification C25D7/00. Mapped technology areas include Chemistry & Metallurgy.
- When was this patent published?
- Publication date Tue Aug 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).