Delay line circuits and semiconductor integrated circuits

Patent metadata

Field	Value
Publication number	US-9432012-B2
Application number	US-201514607230-A
Country	US
Kind code	B2
Filing date	Jan 28, 2015
Priority date	May 29, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

First claim

What is claimed is:

1. A delay line circuit comprising:
a fine delay unit having an input terminal coupled to an input terminal of the delay line circuit and an output terminal coupled to an output terminal of the delay line circuit through a switch; and
a coarse delay unit coupled to the output terminal of the fine delay unit in series, wherein the coarse delay unit is coupled to the output terminal of the delay line circuit through a corresponding one of a plurality of first s…

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Liu Quanfeng
• Duan Huijie

Classifications

• H10W20/43

  Electricity · mapped topic

• H10D84/83138

  Electricity · mapped topic

• H10D84/85

  Electricity · mapped topic

• H03K5/14 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic