Antenna apparatus and method

Patent metadata

Field	Value
Publication number	US-9431369-B2
Application number	US-201213714087-A
Country	US
Kind code	B2
Filing date	Dec 13, 2012
Priority date	Dec 13, 2012
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer.

First claim

What is claimed is:

1. A device comprising:
a semiconductor die embedded in a molding compound layer to form a fan-out package, wherein the fan-out package comprises a first through via extending through the fan-out package and a second through via extending through the fan-out package, and wherein the semiconductor die is between the first through via and the second through via;
a plurality of post passivation interconnects formed over the molding compound layer; and
an antenna structure electrically connected to the semiconductor die through the post passivation interconnects, wherein the antenna structure is formed by a first metal line and a second metal line, and wherein:
the first metal line is over the first through via and extends horizontally beyond sidewalls of the first through via; and
the second metal line is over the second through via and extends horizontally beyond sidewalls of the second through via.

2. The device of claim 1 , wherein:
the plurality of post passivation interconnects are formed over a first side of the semiconductor die; and
the antenna structure is formed above a second side of the semiconductor die, wherein the antenna structure is electrically connected to the plurality of post passivation interconnects through a through via.

3. The device of claim 2 , wherein:
the through via is formed in the molding compound layer.

4. The device of claim 2 , wherein:
a portion of the through via extends through the semiconductor die.

5. A device comprising:
a semiconductor die comprising a plurality of active circuits;
a molding compound layer formed over the semiconductor die, wherein the semiconductor die and the molding compound layer form a fan-out package;
a first through package via, a second through package via and a third through package via formed in the molding compound layer, wherein:
the semiconductor die is between the first through package via and the second through package via; and
the third through package via is between a top surface of the semiconductor die and a top surface of the molding compound layer;

a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer;
a plurality of interconnect structures formed in the first dielectric layer; and
an antenna structure formed on a top surface of the first dielectric layer and electrically connected to the plurality of active circuits through a first via, a metal line, a second via and the third through package via, wherein a top surface of the first via is in direct contact with a bottom surface of the antenna structure and a bottom surface of the first via is in direct contact with a top surface of the metal line, and wherein the antenna structure extends horizontally beyond sidewalls of the first through package via and the second through package via.

6. The device of claim 5 , further comprising:
a second dielectric layer formed on the first dielectric layer over the molding compound layer; and
a post passivation interconnect formed in the second dielectric layer, wherein the antenna structure is electrically connected to the plurality of active circuits through the post passivation interconnect.

7. The device of claim 5 , further comprising:
a second side dielectric layer formed on a second side of the semiconductor die over the molding compound layer; and
a metal bump formed over the second side dielectric layer.

8. The device of claim 5 , wherein:
the antenna structure is formed of copper.

9. The device of claim 5 , wherein:
the antenna structure is of a meander line shape.

10. A method comprising:
embedding a semiconductor die in a molding compound layer;
forming a first group of through vias in the molding compound layer;
forming a first interconnect structure on a first side of the semiconductor die, wherein the first interconnect structure is coupled the semiconductor die through the first group of through vias;
depositing a first dielectric layer over the molding compound layer, wherein the first interconnect structure is embedded in the first dielectric layer;
forming a post passivation interconnect over the first dielectric layer; and
forming an antenna structure above the post passivation interconnect, wherein the antenna structure is electrically connected to the semiconductor die, wherein the antenna structure comprises a first metal line and a second metal line, and wherein the first metal line and the second metal line are placed in a symmetrical manner with respect to the semiconductor die.

11. The method of claim 10 , further comprising:
attaching the semiconductor die on a first carrier;
forming a first side structure above the semiconductor die;
detaching the first carrier from the semiconductor die;
flipping the semiconductor die;
attaching the semiconductor die on a second carrier;
forming a second side structure above the semiconductor die; and
detaching the second carrier from the semiconductor die.

12. The method of claim 10 , further comprising:
coupling the antenna structure with the semiconductor die by using a through via, the first interconnect structure, wherein the through via is formed in the molding compound layer.

13. The method of claim 10 , further comprising:
coupling the antenna structure with the semiconductor die by using a through via, the first interconnect structure, wherein the through via is formed in the semiconductor die.

14. The method of claim 10 , further comprising:
coupling the antenna structure with the semiconductor die through the post passivation interconnect and the first interconnect structure.

15. The method of claim 10 , further comprising:
depositing a second side dielectric layer on a second side of the semiconductor die over the molding compound layer; and
forming a metal bump over the second side dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chih Lai Wei
• Liu Monsen
• Yeh En-Hsiang
• Wang Chuei-Tang
• Yu Chen-Hua

Classifications

• H01Q1/2283 Primary

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title

• H01Q9/0407

  Substantially flat resonant element parallel to ground plane, e.g. patch antenna (dipole H01Q9/285; monopole H01Q9/40) · CPC title

• H01Q1/36

  Structural form of radiating elements, e.g. cone, spiral, umbrella; {Particular materials used therewith}(H01Q1/08, H01Q1/14 take precedence) · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title