Integrated circuit chip customization using backside access

Patent metadata

Field	Value
Publication number	US-9431298-B2
Application number	US-93943910-A
Country	US
Kind code	B2
Filing date	Nov 4, 2010
Priority date	Nov 4, 2010
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.

First claim

The invention claimed is:

1. An apparatus, comprising:
a substrate having a frontside surface and a backside surface;
a programmable element located on said frontside surface; and
a plurality of vias through said substrate configured to provide an electrical connection from said backside surface to said programmable element on said frontside surface, wherein each of said plurality of vias couple to sacrificial contacts on said backside surface, said sacrificial contacts configured to only be used for programming, and wherein said programmable element is configured to be programmed by a programming stimulus selectively applied to said plurality of vias from said sacrificial contacts on said backside surface.

2. The apparatus of claim 1 , wherein said programmable element is an anti-fuse.

3. The apparatus of claim 1 , wherein said programmable element is a fuse.

4. The apparatus of claim 3 , wherein said fuse is a polysilicon fuse.

5. The apparatus of claim 3 , wherein said fuse is a metal fuse.

6. The apparatus of claim 1 , wherein said programmable element is a programmable read-only memory (PROM).

7. The apparatus of claim 1 , wherein said programmable element is a resistive random-access memory (RRAM).

8. The apparatus of claim 1 , wherein said programmable element is a magnetic random-access memory (MRAM).

9. The apparatus of claim 1 , further comprising a conductive layer on said backside surface to facilitate connection to said plurality of vias.

10. The apparatus of claim 9 , wherein said conductive layer comprises copper.

11. The apparatus of claim 9 , wherein said conductive layer comprises tungsten.

12. The apparatus of claim 9 , wherein said conductive layer comprises aluminum.

13. The apparatus of claim 9 , wherein said conductive layer is a metallization layer.

14. The apparatus of claim 1 , wherein said substrate is a material selected from the group consisting of gallium arsenide, indium phosphide, silicon germanium, gallium indium arsenide, silicon on glass, silicon on sapphire, silicon on ceramic, glass, sapphire, ceramic, Bismaleimide-Triazine (BT), epoxy, and epoxy blends.

15. The apparatus of claim 1 , wherein said substrate is a silicon substrate.

16. The apparatus of claim 15 , wherein said plurality of vias are through-silicon-vias (TSVs) formed in said silicon substrate.

17. The apparatus of claim 1 , integrated into a device selected from the group consisting of a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and a fixed location data unit.

18. The apparatus of claim 1 , wherein said programmable element can be programmed by said programming stimulus to one or more of repair said apparatus, effect redundancy in said apparatus, configure functionality of said apparatus, create one or more of a serialization or an identification to uniquify said apparatus, or enable options to integrate said substrate into a three dimensional stack.

19. A method for customizing an integrated circuit, comprising:
providing a substrate having a frontside surface and a backside surface;
forming a plurality of vias through said substrate to provide an electrical connection from said backside surface to a programmable element located on said frontside surface, wherein forming said plurality of vias comprises coupling each of said plurality of vias to sacrificial contacts on said backside surface, said sacrificial contacts configured to only be used for programming; and
applying a programming stimulus to said plurality of vias from said sacrificial contacts on said backside surface to program said programmable element to establish a functionality of said integrated circuit.

20. The method of claim 19 wherein said programmable element is a fuse.

21. The method of claim 19 wherein said programmable element is an antifuse.

22. The method of claim 19 wherein said programmable element is a programmable read-only memory (PROM).

23. The method of claim 19 wherein said programmable element is a resistive random-access memory (RRAM).

24. The method of claim 19 wherein said programmable element is a magnetic random-access memory (MRAM).

25. The method of claim 19 wherein said providing said substrate comprises providing a silicon substrate.

26. The method of claim 25 wherein said forming said plurality of vias comprises forming through-silicon-vias (TSVs) in said silicon substrate.

27. The method of claim 19 wherein said functionality of said integrated circuit includes one or more of a repair of said integrated circuit, redundancy effected in said integrated circuit, a configuration to enable or disable one or more of a function or a block of circuitry, or integration of said substrate into a three dimensional stack.

28. The method of claim 19 wherein said functionality of said integrated circuit includes creating one or more of a serialization or an identification to uniquify said integrated circuit or a serialization or an identification to uniquify said substrate in a three dimensional stack of substrates.

29. A method for customizing an integrated circuit, comprising:
providing a substrate having a frontside surface and a backside surface;
forming conductors through said substrate to provide electrical connections from said backside surface to a programmable element located on said frontside surface, wherein forming said conductors includes coupling each of said conductors to sacrificial contacts on said backside surface, said sacrificial contacts configured to only be used for programming; and
applying a programming stimulus to said conductors from said sacrificial contacts on said backside surface to program said programmable element to uniquify said integrated circuit.

30. The method of claim 29 wherein said programmable element is a fuse.

31. The method of claim 29 wherein said programmable element is an antifuse.

32. The method of claim 29 wherein said programmable element is a programmable read-only memory (PROM).

33. The method of claim 29 wherein said programmable element is a resistive random-access memory (RRAM).

34. The method of claim 29 wherein said programmable element is a magnetic random-access memory (MRAM).

35. The method of claim 29 wherein said substrate comprises a silicon substrate.

36. The method of claim 35 wherein said forming conductors comprises forming through-silicon-vias (TSVs) in said silicon substrate.

37. The method of claim 29 wherein said substrate comprises a material selected from the group consisting of gallium arsenide, indium phosphide, silicon germanium, gallium indium arsenide, silicon on glass, silicon on sapphire, silicon on ceramic, glass, sapphire, ceramic, Bismaleimide-Triazine (BT), epoxy, and epoxy blends.

38. The method of claim 29 wherein applying said programming stimulus to program said programmable element to uniquify said integrated circuit comprises creating one or more of a serialization or an identification of said integrated circuit.

39. The method of claim 38 wherein applying said programming stimulus to program said

Assignees

• Perry Daniel W
• Gu Shiqun
• Qualcomm Inc

Inventors

• Perry Daniel W
• Gu Shiqun

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title