Fin cut for tight fin pitch by two different sit hard mask materials on fin

US9431265B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9431265-B2
Application numberUS-201414499595-A
CountryUS
Kind codeB2
Filing dateSep 29, 2014
Priority dateSep 29, 2014
Publication dateAug 30, 2016
Grant dateAug 30, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired SIT spacers are exposed by the cut mask due to the different etching characteristics of the different materials.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor structure comprising: forming a plurality of mandrel structures on a substrate; forming first spacers on sidewalls of the plurality of mandrel structures; forming sacrificial spacers on sidewalls of the first spacers; forming second spacers on sidewalls of the sacrificial spacers; removing the plurality of mandrel structures and the sacrificial spacers selective to the first spacers and the second spacers; forming a cut mask including at least one opening therein over the first spacers, the second spacers and exposed surfaces of the substrate, the at least one opening exposing portions of the first spacers and portions of the second spacers; removing exposed portions of the first spacers selective to exposed portions of the second spacers; removing the cut mask selective to remaining portions of the first spacers and the second spacers; forming another cut mask including at least one opening therein over the remaining portions of the first spacers, the second spacers and exposed surfaces of the substrate, the at least one opening exposing portions of the remaining portions of the first spacers and portions of second spacers; and removing exposed portions of the second spacers selective to exposed portions of the remaining portions of the first spacers. 2. The method of claim 1 , wherein the removing the plurality of mandrel structures and sacrificial spacers provides a plurality of first spacers and a plurality of second spacers, wherein every adjacent pairs of the first spacers are separated from each other by a corresponding pair of the second spacers. 3. The method of claim 1 , wherein each of the second spacers comprises a material different from a material of each of the first spacers. 4. The method of claim 3 , wherein each of the first spacers comprises a dielectric nitride, and wherein each of the second spacers comprises a high k dielectric material. 5. The method of claim 1 , wherein the removing the exposed portions of the first spacers comprises removing at least one pair of the first spacers located between adjacent pairs of the second spacers. 6. The method of claim 1 , wherein the removing the exposed portions of the second spacers comprises removing at least one pair of the second spacers located between adjacent pairs of the first spacers. 7. The method of claim 1 , further comprising patterning a portion of the substrate utilizing the remaining portions of the first spacers and remaining portions of the second spacers as an etch mask. 8. The method of claim 7 , further comprising removing the remaining portions of the first spacers and the remaining portions of the second spacers after the patterning the portion of the substrate. 9. The method of claim 8 , wherein the portion of the substrate comprises a semiconductor material. 10. The method of claim 1 , wherein the forming the plurality of mandrel structures comprises: depositing a mandrel material layer on an entire topmost surface of the substrate; and patterning the mandrel material layer by lithography and etching. 11. The method of claim 1 , wherein the forming the first spacers on sidewalls of the plurality of mandrel structures comprises: forming a first spacer material layer over the plurality of mandrel structures and exposed surfaces of the substrate; and removing horizontal portions of the first spacer material layer by an anisotropic etch. 12. The method of claim 1 , wherein the forming the sacrificial spacers on sidewalls of the first spacers comprises: forming a sacrificial spacer material layer over the plurality of mandrel structures, the first spacers and exposed surfaces of the substrate; and removing horizontal portions of the sacrificial spacer material layer by an anisotropic etch. 13. The method of claim 1 , wherein the forming the second spacers on sidewalls of the sacrificial spacers comprises: forming a second spacer material layer over the plurality of mandrel structures, the first spacers, the sacrificial spacers and exposed surfaces of the substrate; and removing horizontal portions of the second spacer material layer by an anisotropic etch. 14. The method of claim 1 , wherein each of the plurality of mandrel structures comprises amorphous silicon, and wherein each of the sacrificial spacers comprises amorphous carbon. 15. The method of claim 1 , wherein the first spacers and the second spacers have a substantially same width, and the plurality of the mandrel structure and the sacrificial spacers have a substantially same width.

Assignees

Inventors

Classifications

  • Process specially adapted to improve the resolution of the mask · CPC title

  • H10P50/695Primary

    characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

  • characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

  • characterised by their composition, e.g. multilayer masks or materials · CPC title

  • of Group IV materials · CPC title

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What does patent US9431265B2 cover?
Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10P50/695. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).