One time programming memory cell, array structure and operating method thereof

Patent metadata

Field	Value
Publication number	US-9431111-B2
Application number	US-201414515902-A
Country	US
Kind code	B2
Filing date	Oct 16, 2014
Priority date	Jul 8, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A one time programming memory cell includes a transistor, a first varactor, and a second varactor. The transistor has a gate terminal, a source terminal and a drain terminal. The gate terminal of the transistor is connected with a word line. The source terminal of the transistor is connected with a bit line. A first end of the first varactor is connected with the drain terminal of the transistor. A second end of the first varactor is connected with a first program line. A first end of the second varactor is connected with the drain terminal of the transistor. A second end of the second varactor is connected with a second program line.

First claim

What is claimed is:

1. An operating method of an array structure, the array structure having a first one time programming memory cell comprising: a first transistor having a gate terminal connected with a first word line, a source terminal connected with a first bit line and a drain terminal, a first varactor having a first end connected with the drain terminal of the first transistor and a second end connected with a first program line, and a second varactor having a third end connected with the drain terminal of the first transistor and a fourth end connected with a second program line, the operating method comprising steps of:
performing a first program process to turn the first varactor of the first one time programming memory cell into a first resistor;
performing a verification process to read a first read current of the first one time programming memory cell; and
judging whether the first one time programming memory cell is a failed memory cell according to the first read current, wherein if the first one time programming memory cell is verified as the failed memory cell, a second program process is performed to turn the second varactor of the first one time programming memory cell into a second resistor.

2. The operating method as claimed in claim 1 , wherein if the first read current is lower than a reference current, the first one time programming memory cell is verified as the failed memory cell.

Assignees

• Ememory Technology Inc

Inventors

• Wu Meng-Yi
• Chen Hsin-Ming

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C17/08

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title