Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Patent metadata

Field	Value
Publication number	US-9431084-B2
Application number	US-201414320172-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jan 21, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

First claim

The invention claimed is:

1. A method of managing memory, the method comprising:
determining a performance characteristic of a memory based on a relationship between a bit error rate, a programming pulse width, and one or more of: a temperature, a history-based predictive performance parameter, a coding scheme for data, or a voltage level associated with the memory, wherein the programming pulse width is a length of a pulse used to write the data;
storing the performance characteristic in the memory; and
managing a write operation associated with the memory using the stored performance characteristic, wherein using the performance characteristic includes determining whether to perform at least one of a long write operation, a sequence of short write operations, or a single short write operation.

2. The method of claim 1 , wherein the memory is a spin transfer torque magnetoresistive random-access memory (STT-MRAM).

3. The method of claim 1 , wherein using the performance characteristic further includes varying the programming pulse width.

4. The method of claim 1 , wherein using the performance characteristic further includes varying the coding scheme.

5. The method of claim 1 , further comprising determining the bit error rate of the memory.

6. The method of claim 1 , further comprising detecting the temperature of the memory.

7. The method of claim 1 , further comprising determining the performance characteristic at runtime.

8. The method of claim 1 , further comprising determining the performance characteristic at test time.

9. The method of claim 1 , wherein the history-based predictive performance parameter is associated with past performance of the memory.

10. The method of claim 1 , further comprising determining the performance characteristic at the memory, wherein the memory is coupled to a main memory controller.

11. The method of claim 1 , further comprising determining whether the memory supports the long write operation.

12. The method of claim 1 , further comprising determining a number of data flips associated with data.

13. A method of managing memory, the method comprising:
determining a performance characteristic of a memory based on a relationship between two or more of: a bit error rate, a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme for data, or a voltage level associated with the memory, wherein the programming pulse width is a length of a pulse used to write the data;
storing the performance characteristic in the memory; and
managing a write operation associated with the memory based on the performance characteristic and based on a number of data flips that are to be performed in response to a determination that the temperature is above a first threshold value, wherein the number of data flips is based on an exclusive-OR operation; and
determining the programming pulse width and subsequently performing one of: a long write operation in response to a determination that the number of data flips is greater than a second threshold value or a short write operation in response to a determination that the number of data flips is less than the second threshold value.

14. The method of claim 13 , further comprising varying the coding scheme for data to be written to the memory using the performance characteristic.

15. A method of managing memory, the method comprising:
determining a performance characteristic of a memory based on a relationship between a programming pulse width, and one or more of: a bit error rate, a temperature, a history-based predictive performance parameter, a coding scheme for data, or a voltage level associated with the memory, wherein the programming pulse width is a length of a pulse used to write the data;
storing the performance characteristic in the memory;
managing a write operation associated with the memory based on the performance characteristic and based on a number of data flips that are to be performed in response to a determination that the temperature is above a first threshold value, wherein the number of data flips is based on an exclusive-OR operation; and
determining the programming pulse width and subsequently performing one of: a long write operation in response to a determination that the number of data flips is greater than a second threshold value or a short write operation in response to a determination that the number of data flips is less than the second threshold value.

Assignees

• IBM

Inventors

• Bose Pradip
• Buyuktosunoglu Alper
• Guo Xiaochen
• Hunter Hillery C
• Rivers Jude A
• Srinivasan Vijayalakshmi

Classifications

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title