Method and apparatus for automatic relative placement generation for clock trees

Patent metadata

Field	Value
Publication number	US-9430601-B2
Application number	US-201514659126-A
Country	US
Kind code	B2
Filing date	Mar 16, 2015
Priority date	Aug 17, 2011
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design.

First claim

What is claimed is:

1. A system for circuit design, comprising:
an EDA system performing a transformation of a hardware description language circuit representation into a physical circuit representation with a clock tree of clock network flip-flops,
wherein the EDA system complies with a plurality of sets of rules created at different times, and
wherein the EDA system adds clock network buffer circuitry, including an instance with the clock network flip-flops having integrated clock gating,
wherein the system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis.

2. The system of claim 1 , wherein the plurality of sets of rules includes:
a first set of rules guiding coarse placement during the transformation specifically and automatically for a set of circuit elements in a netlist during the transformation including clock network flip-flops, the first set of rules specifying positioning of each circuit element of the set of circuit elements relative to other circuit elements of the set of circuit elements; and
a second set of rules guiding placement of the clock network flip-flops after the coarse placement and before clock tree synthesis.

3. The system of claim 1 , wherein the system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis based on clock sinks.

4. The system of claim 2 , wherein the system automatically groups the clock network flip-flops into a plurality of flip-flop groups after coarse placement and before clock tree synthesis.

5. The system of claim 4 , wherein the second set of rules are based on the plurality of flip-flop groups.

6. The system of claim 4 , wherein the system performs clock tree clustering that automatically groups the clock network flip-flops into the plurality of flip-flop groups.

7. The system of claim 6 , wherein the system performs the clock tree clustering without creating clock network buffer circuitry.

8. The system of claim 6 , wherein the second set of rules are based on the plurality of flip-flop groups from the clock tree clustering.

9. The system of claim 5 , wherein the system automatically creating clock network buffer circuitry for the plurality of flip-flop groups during the placement after the coarse placement.

10. The system of claim 6 , wherein the system automatically creating clock network buffer circuitry for the plurality of flip-flop groups during the placement after the coarse placement, the clock network buffer circuitry matched to the grouped clock network flip-flops in the circuit design.

11. The system of claim 2 , wherein the clock network flip-flops are leaf nodes of a clock tree.

12. The system of claim 1 , wherein the plurality of sets of rules obey clock tree constraints.

13. A tangible non-transitory computer readable medium with computer readable instructions executable by a computer system, comprising:
instructions executable by the computer system to transform a hardware description language circuit representation into a physical circuit representation with a clock tree of clock network flip-flops,
wherein the instructions comply with a plurality of sets of rules created at different times, and
wherein the instructions add clock network buffer circuitry, including an instance with the clock network flip-flops having integrated clock gating,
wherein the computer system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis.

14. The tangible non-transitory computer readable medium of claim 13 , wherein the plurality of sets of rules includes:
a first set of rules guiding coarse placement during the transformation specifically and automatically for a set of circuit elements in a netlist during the transformation including clock network flip-flops, the first set of rules specifying positioning of each circuit element of the set of circuit elements relative to other circuit elements of the set of circuit elements; and
a second set of rules guiding placement of the clock network flip-flops after the coarse placement and before clock tree synthesis.

15. The tangible non-transitory computer readable medium of claim 1 , wherein the computer system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis based on clock sinks.

16. The tangible non-transitory computer readable medium of claim 14 , wherein the computer system automatically groups the clock network flip-flops into a plurality of flip-flop groups after coarse placement and before clock tree synthesis.

17. The tangible non-transitory computer readable medium of claim 16 , wherein the second set of rules are based on the plurality of flip-flop groups.

18. The tangible non-transitory computer readable medium of claim 16 , wherein the computer system performs clock tree clustering that automatically groups the clock network flip-flops into the plurality of flip-flop groups.

19. The tangible non-transitory computer readable medium of claim 18 , wherein the computer system performs the clock tree clustering without creating clock network buffer circuitry.

20. The tangible non-transitory computer readable medium of claim 18 , wherein the second set of rules are based on the plurality of flip-flop groups from the clock tree clustering.

21. The tangible non-transitory computer readable medium of claim 17 , wherein the computer system automatically creating clock network buffer circuitry for the plurality of flip-flop groups during the placement after the coarse placement.

22. The tangible non-transitory computer readable medium of claim 18 , wherein the computer system automatically creating clock network buffer circuitry for the plurality of flip-flop groups during the placement after the coarse placement, the clock network buffer circuitry matched to the grouped clock network flip-flops in the circuit design.

23. The tangible non-transitory computer readable medium of claim 14 , wherein the clock network flip-flops are leaf nodes of a clock tree.

24. The tangible non-transitory computer readable medium of claim 13 , wherein the plurality of sets of rules obey clock tree constraints.

Assignees

• Synopsys Inc

Inventors

• Arunachalam Anand

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic

• G06F2217/62

  Physics · mapped topic