Scheduler, multi-core processor system, and scheduling method

Patent metadata

Field	Value
Publication number	US-9430388-B2
Application number	US-201514601978-A
Country	US
Kind code	B2
Filing date	Jan 21, 2015
Priority date	Aug 27, 2010
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

First claim

What is claimed is:

1. A multi-core processor system comprising:
a plurality of cores configured to execute a plurality of tasks, respectively; and
a plurality of caches configured to store data accessed by the cores when the cores execute the tasks, respectively,
wherein a first core of the cores stores, when a priority of a task assigned to any one of the cores is greater than or equal to a given value, the data into a cache corresponding to the core before the core to which the task is assigned executes the task; and
wherein the first core assigns, among tasks each of which has a priority greater than or equal to the given value, tasks that access identical data to an identical core of the cores.

2. The multi-core processor system according to claim 1 , wherein the first core further prohibits, until execution of the task having the priority greater than or equal to the given value is completed, overwriting of data accessed by the task with other data.

3. A control method of a multi-core processor system that includes a plurality of cores configured to execute a plurality of tasks, respectively, and a plurality of caches configured to store data accessed by the cores when the cores execute the tasks, respectively, wherein a first core of the cores executes a process comprising:
determining if a priority of a task assigned to any one of the cores is greater than or equal to a given value; and
storing, when the priority of the task is determined to be greater than or equal to the given value, the data into a cache corresponding to the core to which the task is assigned before the core executes the task, and
assigning, among tasks each of which has a priority greater than or equal to the given value, tasks that access identical data to an identical core of the cores.

4. The control method of the multi-core processor system according to claim 3 , wherein the first core further executes prohibiting, until execution of the task having the priority greater than or equal to the given value has been completed, overwriting of data accessed by the task.

Assignees

• Fujitsu Ltd

Inventors

• Yamauchi Hiromasa
• Yamashita Koichiro
• Suzuki Takahisa
• Kurihara Koji

Classifications

• B29C49/42087

  holding outside the neck · CPC title

• B29C49/18

  using several blowing steps (B29C49/16 takes precedence) · CPC title

• G06F9/544 Primary

  Buffers; Shared memory; Pipes · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title