Display panel and display device

Patent metadata

Field	Value
Publication number	US-9429802-B2
Application number	US-201414498470-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	May 14, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A display panel and a display device are provided, and the display panel comprises a GOA circuit; a first conducting wire and a second conducting wire are disposed in a region outside the GOA circuit; an insulating layer is disposed between the first conducting wire and the second conducting wire; and the first conducting wire, the insulating layer and the second conducting wire form a first capacitor. The display panel can protect the internal signal lines of the GOA circuit and the display panel, and increase the antistatic ability of the display panel and the yield of products.

First claim

The invention claimed is:

1. A display panel, comprising a GOA circuit, an array substrate and an opposed substrate, wherein a first conducting wire and a second conducting wire are disposed in a region outside the GOA circuit, an insulating layer is disposed between the first conducting wire and the second conducting wire, and the first conducting wire, the insulating layer and the second conducting wire form a first capacitor;
the first capacitor is provided on the array substrate,
a spacer is further disposed outside the GOA circuit on the opposed substrate, a conductive layer is disposed on a surface and periphery of the spacer, and the conductive layer is disposed opposite to a region where the first capacitor is located on the array substrate; and
a passivation layer is further disposed on the array substrate, and the conductive layer, the passivation layer and the first conducting wire at a corresponding position on the array substrate form a second capacitor.

2. The display panel as claimed in claim 1 , wherein each of the first conducting wire and the second conducting wire comprises a first part and a second part, a width of the first part is greater than that of the second part, and the insulating layer is disposed between the first part of the first conducting wire and the first part of the second conducting wire.

3. The display panel as claimed in claim 1 , wherein a gate electrode, a gate insulating layer and source/drain electrodes are disposed on the array substrate; and the first conducting wire and the source/drain electrodes are formed in a same layer, the second conducting wire and the gate electrode are formed in a same layer, and the insulating layer and the gate insulating layer are formed in a same layer.

4. The display panel as claimed in claim 3 , wherein the first conducting wire and the second conducting wire are not equidistant from the GOA circuit.

5. The display panel as claimed in claim 4 , wherein a distance from the first conducting wire to the GOA circuit is smaller than that from the second conducting wire to the GOA circuit.

6. The display panel as claimed in claim 3 , wherein the first conducting wire and the second conducting wire are equidistant from the GOA circuit.

7. The display panel as claimed in claim 3 , wherein a common electrode line and a ground wire are further disposed on the array substrate; and
the first conducting wire and the second conducting wire are in a dangling state, or the first conducting wire and the second conducting wire are connected to the ground wire or the common electrode line.

8. The display panel as claimed in claim 4 , further comprising a common electrode line and a ground wire, wherein the first conducting wire and the second conducting wire are in a dangling state, or the first conducting wire and the second conducting wire are connected to the ground wire or the common electrode line.

9. The display panel as claimed in claim 6 , further comprising a common electrode line and a ground wire, wherein the first conducting wire and the second conducting wire are in a dangling state, or the first conducting wire and the second conducting wire are connected to the ground wire or the common electrode line.

10. The display panel as claimed in claim 1 , further comprising a common electrode line and a ground wire, wherein the first conducting wire, the second conducting wire and the conductive layer are in a dangling state, or the first conducting wire, the second conducting wire and the conductive layer are connected to the ground wire or the common electrode line.

11. A display device, comprising the display panel as claimed in claim 1 .

12. The display panel as claimed in claim 1 , wherein the display panel comprises a display area, the GOA circuit is provided outside of the display area, and the first capacitor is provided on side of the GOA circuit opposite to the display area.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Fang Yezhou
• Ren Jian
• Wang Zhenwei
• Ding Jinbo
• Li Jian
• Li Bin
• Li Xin

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title