Package architecture utilizing wafer to wafer bonding
US-2024379487-A1 · Nov 14, 2024 · US
Power module
US9426915B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9426915-B2 |
| Application number | US-201314654159-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 20, 2013 |
| Priority date | Dec 25, 2012 |
| Publication date | Aug 23, 2016 |
| Grant date | Aug 23, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
In a power module according to the present invention, a copper layer composed of copper or a copper alloy is provided at a surface of a circuit layer onto which a semiconductor element is bonded, and a solder layer formed by using a solder material is formed between the circuit layer and the semiconductor element. An alloy layer containing Sn as a main component, 0.5% by mass or more and 10% by mass or less of Ni, and 30% by mass or more and 40% by mass or less of Cu is formed at the interface between the solder layer and the circuit layer, the thickness of the alloy layer is set to be within a range of 2 μm or more and 20 μm or less, and a thermal resistance increase rate is less than 10% after loading a power cycles 100,000 times under a condition where an energization time is 5 seconds and a temperature difference is 80° C. in a power cycle test.
First claim
Opening claim text (preview).
The invention claimed is: 1. A power module comprising: a power module substrate provided with a circuit layer on one surface of an insulating layer; and a semiconductor element bonded onto the circuit layer, wherein a copper layer composed of copper or a copper alloy is provided on the surface of the circuit layer onto which the semiconductor element is bonded, a solder layer formed by using a solder material is formed between the circuit layer and the semiconductor element, an alloy layer containing Sn as a main component, 0.5% by mass or more and 10% by mass or less of Ni, and 30% by mass or more and 40% by mass or less of Cu is formed at an interface between the solder layer and the circuit layer, a thickness of the alloy layer is set to be within a range of 2 μm or more and 20 μm or less, and a thermal resistance increase rate is less than 10% after loading power cycles 100,000 times under the condition where an energization time is 5 seconds and a temperature difference is 80° C. in a power cycle test. 2. The power module according to claim 1 , wherein the alloy layer includes an intermetallic compound composed of (Cu,Ni) 6 Sn 5 .
Assignees
Inventors
Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
the semiconductor body being completely enclosed · CPC title
changes in materials · CPC title
Soldering or alloying · CPC title
Intermetallic compounds · CPC title
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- What does patent US9426915B2 cover?
- In a power module according to the present invention, a copper layer composed of copper or a copper alloy is provided at a surface of a circuit layer onto which a semiconductor element is bonded, and a solder layer formed by using a solder material is formed between the circuit layer and the semiconductor element. An alloy layer containing Sn as a main component, 0.5% by mass or more and 10% by…
- Who is the assignee on this patent?
- Mitsubishi Materials Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W40/255. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).