DC-DC converter incorporating trim cell

US9425749B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9425749-B2
Application numberUS-201314034053-A
CountryUS
Kind codeB2
Filing dateSep 23, 2013
Priority dateSep 23, 2012
Publication dateAug 23, 2016
Grant dateAug 23, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

First claim

Opening claim text (preview).

What is claimed is: 1. A DC-DC converter, comprising: a switching circuit coupled to a DC voltage source and operative to convert an input voltage value into an output voltage value across an output capacitor in accordance with a reference voltage; a feedback circuit coupled to said switching circuit and operative to generate a drive signal for said switching circuit; a trim cell incorporating a trim capacitor coupled to said output capacitor and operative to be connected in series with said output capacitor in accordance with a trim control signal thereby increasing said output voltage substantially instantaneously; and wherein at least one of the following is true: (a) the DC-DC converter comprises an error amplifier that is configured to generate an error signal based on a difference between said reference signal and a sampled voltage, wherein the sampled voltage equals said output voltage multiplied by a voltage divider ratio, wherein the voltage divider ratio equals a ratio between a resistance of a second resistor and divided by a sum of resistances of a first resistor and the second resistor; and (b) during a steady state mode the trim capacitor is configured to be disconnected from said output capacitor, disconnected from an output port of the DC-DC converter and charged to a trim voltage by a trim buffer that receives the trim voltage from a trim control block and is configured to be coupled to said output capacitor. 2. The DC-DC converter according to claim 1 , wherein said switching circuit comprises a synchronous DC-DC converter circuit selected from the group consisting of buck, boost and forward. 3. The DC-DC converter according to claim 1 , wherein said feedback circuit comprises the error amplifier and a pulse width modulation (PWM) comparator configured to generate a PWM signal in accordance with said error signal and an oscillator input signal. 4. The DC-DC converter according to claim 3 , wherein said oscillator signal comprises a triangle or saw-tooth signal. 5. The DC-DC converter according to claim 1 , wherein said trim capacitor is normally charged to a trim voltage which is added to said output voltage in response to a trim up control signal, said output voltage transitioning substantially instantaneously due to there being no need to charge said output capacitor and said trim capacitor. 6. The DC-DC converter according to claim 1 , wherein said trim capacitor normally charged to a trim voltage and adapted to be connected in series with said output capacitor in response to a trim up control signal, said output voltage transitioning substantially instantaneously due to there being no need to charge said output capacitor and said trim capacitor. 7. The DC-DC converter according to claim 1 , wherein said reference voltage is adjusted up by a predetermined amount in response to a trim up control signal so as to maintain said feedback circuit in steady state condition. 8. The DC-DC converter according to claim 1 , wherein said trim capacitor is normally charged to a trim voltage which is subtracted from said output voltage in response to a trim down control signal. 9. The DC-DC converter according to claim 1 , wherein said trim capacitor is normally charged to a trim voltage and adapted to be disconnected from said output capacitor in response to a trim down control signal. 10. The DC-DC converter according to claim 1 , wherein said reference voltage is adjusted down by a predetermined amount in response to a trim down control signal so as to maintain said feedback circuit in steady state condition. 11. The DC-DC converter according to claim 1 , wherein said DC-DC converter is adapted to provide a supply voltage to a power amplifier configured to transmit signals conforming to a wireless standard selected from the group consisting of 802.11 WLAN, LTE, WiMAX, HDTV, 3G cellular, 40 cellular and DECT. 12. A DC-DC converter, comprising: a switching circuit coupled to a DC voltage source and operative to convert an input voltage value into an output voltage value across an output capacitor in accordance with a reference voltage; a feedback circuit coupled to said switching circuit and operative to generate a drive signal for said switching circuit; a trim cell coupled to said output capacitor, said trim cell comprising: a first switch connecting said output capacitor to ground; a trim buffer operative to charge a trim capacitor to a trim voltage; a second switch connecting said trim capacitor to said output capacitor in series; and trim control logic operative to control said first switch and said second switch in accordance with a trim control command; and wherein at least one of the following is true: (a) the DC-DC converter comprises an error amplifier that is configured to generate an error signal based on a difference between said reference signal and a sampled voltage, wherein the sampled voltage equals said output voltage multiplied by a voltage divider ratio, wherein the voltage divider ratio equals a ratio between a resistance of a second resistor and divided by a sum of resistances of a first resistor and the second resistor; and (b) the trim buffer comprises a operational amplifier having a non-inverting input that receives the trim voltage from the trim control logic and a non-inverting input that is coupled to an output of the operational amplifier. 13. The DC-DC converter according to claim 12 , wherein said switching circuit comprises a synchronous DC-DC converter circuit selected from the group consisting of buck, boost and forward. 14. The DC-DC converter according to claim 12 , wherein said feedback circuit comprises the error amplifier and a pulse width modulation (PWM) comparator configured to generate a PWM signal in accordance with said error signal and an oscillator input signal. 15. The DC-DC converter according to claim 14 , wherein said oscillator signal comprises a triangle or saw-tooth signal. 16. The DC-DC converter according to claim 12 , wherein in response to a trim up command, said trim control logic is operative to open said first switch and close said second switch thereby adding a trim voltage on said trim capacitor to said output voltage, said output voltage transitioning substantially instantaneously due to there being no need to charge said output capacitor and said trim capacitor. 17. The DC-DC converter according to claim 12 , wherein said reference voltage is adjusted up by a predetermined amount in response to a trim up control signal so as to maintain said feedback circuit in steady state condition. 18. The DC-DC converter according to claim 12 , wherein in response to a trim down command, said trim control logic is operative to close said first switch and open said second switch thereby disconnecting said trim capacitor and lowering said output voltage by said trim voltage. 19. The DC-DC converter according to claim 12 , wherein said reference voltage is adjusted down by a predetermined amount in response to a trim down control signal so as to maintain said feedback circuit in steady state condition. 20. The DC-DC converter according to claim 12 , wherein said DC-DC converter is adapted to provide a supply voltage to a power amplifier configured to transmit signals conforming to a wireless standard selected from the group consisting of 802.11 WLAN, LTE, WiMAX, HDTV, 3G cellular, 4G cellular and DECT. 21. A DC-DC converter, comprising: a switching circuit coupled to a DC voltage source and operative to convert an input voltage value into an output voltage value acr

Assignees

Inventors

Classifications

  • being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

  • for passive devices or passive elements · CPC title

  • Arrangements for impedance matching · CPC title

  • Wires · CPC title

  • Inductive arrangements (H10W44/20 takes precedence) · CPC title

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Frequently asked questions

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What does patent US9425749B2 cover?
A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as st…
Who is the assignee on this patent?
Dsp Group Ltd, Dsp Group Ltd
What technology area does this patent fall under?
Primary CPC classification H03F1/565. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 23 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).