Insulated-gate bipolar transistor

Patent metadata

Field	Value
Publication number	US-9425271-B2
Application number	US-201214002752-A
Country	US
Kind code	B2
Filing date	Mar 7, 2012
Priority date	Mar 9, 2011
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

In an IGBT, a trench extending in a bent shape to have a corner is formed in an upper surface of a semiconductor substrate. The inside of the trench is covered with an insulating film. A gate is placed inside the trench. An emitter and a collector are formed on an upper surface and a lower surface of the semiconductor substrate, respectively. An emitter region, a body region, a drift region, and a collector region are formed in the semiconductor substrate. The emitter region is formed of an n-type semiconductor, is in contact with the insulating film, and is in ohmic contact with the emitter electrode. The body region is formed of a p-type semiconductor, is in contact with the insulating film below the emitter region, is in contact with the insulating film of an inner corner portion of the trench, and is in ohmic contact with the emitter electrode.

First claim

The invention claimed is:

1. An insulated-gate bipolar transistor (IGBT) comprising:
a semiconductor substrate;
an emitter electrode;
a collector electrode; and
a gate electrode, wherein:
a trench that is formed in a first major surface of the semiconductor substrate, which is one major surface of the semiconductor substrate, the trench extending in a bent shape to have a corner in a plan view of the semiconductor substrate on a first major surface side, the trench defining a rectangular region in the plan view of the semiconductor substrate on the first major surface side;
an inside surface of the trench is covered with an insulating film;
the gate electrode is placed inside the trench;
the emitter electrode is formed on the first major surface of the semiconductor substrate;
the collector electrode is formed on a second major surface of the semiconductor substrate, which is another major surface of the semiconductor substrate; and
the semiconductor substrate includes therein:
an emitter region that is formed of an n-type semiconductor, is in contact with the insulating film, and is in ohmic contact with the emitter electrode;
a body region that is formed of a p-type semiconductor, is in contact with the insulating film at a position adjacent to the emitter region and is in contact with the insulating film at an inside corner portion of the trench, and is in ohmic contact with the emitter electrode;
a drift region that is formed of an n-type semiconductor, is formed on a side closer to the second major surface with respect to the body region, is separated from the emitter region by the body region, and is in contact with the insulating film at a second major surface-side end portion of the trench; and
a collector region that is formed of a p-type semiconductor, is formed on a side closer to the second major surface with respect to the drift region, is separated from the body region by the drift region, and is in ohmic contact with the collector electrode; and

a high concentration n-type region is formed between a portion of the body region and the drift region, wherein the high concentration n-type region is formed of an n-type semiconductor, and is separated from the emitter region by the body region, and the high concentration n-type region separates the portion of the body region from the drift region, and is higher in concentration of n-type impurity than the drift region, and
the emitter region and the body region are formed in the rectangular region, in the rectangular region in the plan view of the semiconductor substrate, a total length of a boundary line where the emitter region is in contact with the insulating film is shorter than a total length of a boundary line where the body region is in contact with the insulating film,
in the plan view of the semiconductor substrate, the body region includes a first body region portion and a second body region portion, the first body region portion extending along an entire length between a first corner and a second corner of the rectangular region, and the second body region portion extending along an entire length between a third corner and a fourth corner of the rectangular region, and the emitter region includes no more than a first emitter portion and a second emitter portion, the first emitter portion separating the first body region portion from the second body region portion between the first corner and the third corner of the rectangular region, and the second emitter portion separating the first body region portion from the second body region portion between the second corner and the fourth corner of the rectangular region, and
wherein the high concentration n-type region is a barrier region that separates the body region into a first major surface-side body region and a second major surface-side body region;
the first major surface-side body region is in contact with the emitter region;
the barrier region is formed of an n-type semiconductor, and is formed on a side closer to the second major surface with respect to the first major surface-side body region; and
the second major surface-side body region is formed on a side closer to the second major surface with respect to the barrier region.

2. The IGBT according to claim 1 , wherein
the high concentration n-type region is in contact with the body region and is in contact with the drift region.

3. The IGBT according to claim 1 , wherein:
the body region has a first region that is in ohmic contact with the emitter electrode, and a second region that is electrically continuous with the emitter electrode through the first region;
the first region is not in contact with the insulating film;
the second region is in contact with the insulating film; and
the emitter region is not in contact with the insulating film of the inside corner portion of the trench.

4. The IGBT according to claim 1 , wherein
a plurality of the rectangular regions are aligned in a first direction and are staggered in a second direction that is orthogonal to the first direction by alternately shifting the rectangular regions by an amount of half a dimension of each of the rectangular regions along the first direction, and
a ratio of the dimension along the first direction to a dimension of each of the rectangular regions along the second direction is within a range between 0.4 and 2.5 inclusive.

5. The IGBT according to claim 1 , wherein:
a plurality of rectangular regions are aligned in a first direction and are staggered in a second direction that is orthogonal to the first direction by alternately shifting the rectangular regions by an amount of half a dimension of each of the rectangular regions along the first direction;
the emitter region and the body region are formed in each of the plurality of rectangular regions; and
a ratio of the dimension along the first direction to a dimension of each of the rectangular regions along the second direction is within a range between 0.4 and 2.5 inclusive.

6. The IGBT according to claim 1 , wherein the rectangular region is square.

7. The IGBT according to claim 1 , wherein the trench is bent at an angle of 90 degrees at the corner in the plan view.

8. The IGBT according to claim 5 , wherein:
the plurality of rectangular regions are defined by the trench in the plan view of the semiconductor substrate on the first major surface side;
the plurality of rectangular regions are aligned in a first direction and are staggered in a second direction that is orthogonal to the first direction by alternately shifting the rectangular regions by an amount of half a dimension of each of the rectangular regions along the first direction;
the emitter region and the body region are formed in each of the plurality of rectangular regions; and
a ratio of the dimension along the first direction to a dimension of each of the rectangular regions along the second direction is within a range between 0.4 and 2.5 inclusive.

Assignees

• Saito Jun
• Machida Satoru
• Toyota Motor Co Ltd

Inventors

• Saito Jun
• Machida Satoru

Classifications

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/107

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title