Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9425198-B2
Application number	US-201414289672-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	Jun 7, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a strain-relaxed buffer layer having a p-type impurity on the substrate;
a first channel layer on the strain-relaxed buffer layer and located in a first region of the device;
an n-type well in the strain-relaxed buffer layer and located in a second region of the device;
a second channel layer on an upper bound of the n-type well;
a gate dielectric disposed directly on the first and second channel layers;
a device isolation region comprising insulation material in the strain-relaxed buffer layer at a boundary between the first region and the second region; and
wherein a lattice constant of the first channel layer is less than a lattice constant of the strain-relaxed buffer layer, but a lattice constant of the second channel layer is greater than said lattice constant of the strain-relaxed buffer layer,
the bottom surface of the device isolation region is disposed above the upper surface of the substrate, and
the lowermost bound of said n-type well is disposed at a level above the substrate and below the level of the bottom surface of the device isolation region.

2. The semiconductor device as claimed in claim 1 , wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).

3. The semiconductor device as claimed in claim 1 , wherein the first and second channel layers each have a thickness of 25 to 35 nm.

4. The semiconductor device as claimed in claim 1 , wherein the strain-relaxed buffer layer comprises Si (1-x) Ge x , the first channel layer comprises Si (1-y) Ge y , and the second channel layer comprises Si (1-z) Ge z ,
wherein y and z are greater than or equal to 0 but less than or equal to 1; and
wherein x is greater than y but less than z.

5. A semiconductor device, comprising:
a substrate;
a strain-relaxed buffer layer having a p-type impurity on the substrate;
a source and a drain of an NMOS transistor, a first channel layer disposed on the strain-relaxed buffer layer and extending in a lengthwise direction between the source and drain of the NMOS transistor, and a gate electrode of the NMOS transistor disposed on the first channel layer; and
a source and a drain of a PMOS transistor, a second channel layer disposed on the strain-relaxed buffer layer and extending in a lengthwise direction between the source and drain of the PMOS transistor, and a gate electrode of the PMOS transistor disposed on the second channel layer, and
wherein a lattice constant of the first channel layer is less than a lattice constant of the strain-relaxed buffer layer, and a lattice constant of the second channel layer is greater than said lattice constant of the strain-relaxed buffer layer, and
the source and drain of the NMOS transistor, the source and drain of the PMOS transistor, the first channel layer, and the second channel layer have upper surfaces, respectively, that are coplanar,
the semiconductor device further comprises a device isolation region comprising insulation material in the strain-relaxed buffer layer at a boundary between the NMOS transistor and the PMOS transistor, and
the strain-relaxed buffer layer has at least one well containing a dopant of a respective conductivity type, a respective one of said channel layers is disposed on each said well, the bottom surface of the device isolation region is disposed above the upper surface of the substrate, and the lowermost bound of each said well is disposed at a level below the level of the bottom surface of the device isolation region.

6. The semiconductor device as claimed in claim 5 , wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).

7. The semiconductor device as claimed in claim 6 , wherein the first channel layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and silicon (Si).

8. The semiconductor device as claimed in claim 6 , wherein the second channel layer comprises at least one material selected from the group consisting of compounds including a semiconductor from group 3, 4 or 5, silicon germanium (SiGe), and germanium (Ge).

9. The semiconductor device as claimed in claim 5 , wherein the strain-relaxed buffer layer comprises Si (1-x) GE x , the first channel layer comprises Si (1-y) Ge y , and the second channel layer comprises Si (1-z) Ge z ,
wherein y and z are greater than or equal to 0 but less than or equal to 1, respectively, and
x is greater than y but less than z.

10. The semiconductor device as claimed in claim 9 , wherein x minus y is in a range of 0.2 to 0.4.

11. The semiconductor device as claimed in claim 1 , wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs).

12. The semiconductor device as claimed in claim 4 , wherein x minus y is in a range of 0.2 to 0.4, and z-x is a range of 0.2 to 0.4.

13. The semiconductor device as claimed in claim 5 , wherein the strain-relaxed buffer layer comprises at least one material selected from the group consisting of gallium arsenic antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium antimonide (GaSb), and indium arsenide (InAs).

14. The semiconductor device as claimed in claim 5 , wherein the strain-relaxed buffer layer has at least one well containing a dopant of a respective conductivity type,
a respective one of said channel layers is disposed on each said well, the bottom surface of the device isolation region is disposed above the upper surface of the substrate, and
the lowermost bound of each said well is disposed at a level above the substrate and below the level of the bottom surface of the device isolation region.

15. The semiconductor device as claimed in claim 10 , wherein z minus x is in a range of 0.2 to 0.4.

16. The semiconductor device as claimed in claim 1 , wherein the first channel layer, and the second channel layer and the device isolation layer have upper surfaces, respectively, that are coplanar.

17. The semiconductor device as claimed in claim 1 , wherein the upper bound of the n-type well and the lowermost bound of the second channel region are both disposed at a level below that of the upper surface of the device isolation region.

Assignees

• Lee Dong-Kyu
• Lee Jae-Hwan
• Kwon Tae-Yong
• Kim Sang-Su
• Choi Jung-Dal
• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Kyu
• Lee Jae-Hwan
• Kwon Tae-Yong
• Kim Sang-Su
• Choi Jung-Dal

Classifications

• H10D30/751

  having composition variations in the channel regions · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/0167 Primary

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title