Methods for performing extended wafer-level packaging (eWLP) and eWLP devices made by the methods

Patent metadata

Field	Value
Publication number	US-9425175-B2
Application number	US-201615002333-A
Country	US
Kind code	B2
Filing date	Jan 20, 2016
Priority date	Mar 14, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Embedded Wafer-Level Packaging (eWLP) devices, packages and assemblies and methods of making them are provided. The eWLP methods allow back side electrical and/or thermal connections to be easily and economically made at the eWLP wafer level without having to use thru-mold vias (TMVs) or thru-silicon vias (TSVs) to make such connections. In order to create TMVs, processes such as reactive ion etching or laser drilling followed metallization are needed, which present difficulties and increase costs. In addition, the eWLP methods allow electrical and optical interfaces to be easily and economically formed on the front side and/or on the back side of the eWLP wafer, which allows the eWLP methods to be used to form optoelectronic devices having a variety of useful configurations.

First claim

What is claimed is:

1. An embedded Wafer-Level Packaging (eWLP) package comprising:
at least first and second chips encapsulated inside of a molded material, the molded material having a front side and a back side, the front side of the molded material being co-planar with respective front sides of the first and second chips, a back side of the molded material being parallel to the front side of the molded material, the first and second chips having respective first electrical contacts disposed on respective front sides of the first and second chips and exposed thru the front side of the molded material, the first chip having at least one second electrical contact disposed on a back side of the first chip; and
a metal layer disposed on the back side of the molded material, the second electrical contact disposed on the back side of the first chip being electrically coupled to the metal layer, the back side of the second chip being in contact with the metal layer, and wherein the second chip comprises a bulk material having a predetermined electrical conductivity that is sufficiently high for conducting electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip.

2. The eWLP package of claim 1 , wherein the first chip is an electrical-to-optical converter (EO) chip for converting an electrical signal into an optical signal and wherein the second chip comprises a combination of an EO driver for driving the EO chip and an optical-to-electrical (OE) converter for converting an optical signal received by the second chip into an electrical signal.

3. The eWLP package of claim 2 , wherein the EO chip is a light-emitting diode (LED) chip, the EO driver is an LED driver and the OE converter is a photodiode.

4. The eWLP package of claim 2 , wherein the EO chip is a laser diode chip, the EO driver is a laser diode driver and the OE converter is a photodiode.

5. The eWLP package of claim 1 , wherein a purpose of the second chip is to conduct electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip such that an electrical connection is made via the second chip and the metal layer to said at least one second electrical contact disposed on the back side of the first chip.

6. The eWLP package of claim 1 , further comprising:
at least a third chip encapsulated inside of the molded material such that the front side of the molded material is co-planar with a front side of the third chip, the third chip having at least one first electrical contact disposed on the front side thereof and exposed thru the front side of the molded material, the third chip having at least one second electrical contact disposed on a back side of the third chip, and wherein the metal layer disposed on the back side of the molded material is electrically coupled to the second electrical contact disposed on the back side of the third chip.

7. The eWLP package of claim 6 , wherein a purpose of the second chip is to conduct electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip such that an electrical connection is made via the second chip and the metal layer to said at least one second electrical contact disposed on the back side of the first chip.

8. The eWLP package of claim 7 , wherein the first chip is an optical-to-electrical (OE) converter chip for converting an optical signal into an electrical signal, and wherein the third chip is a receiver chip for processing the electrical signal.

9. The eWLP package of claim 7 , wherein the first chip is an electrical-to-optical (EO) converter chip for converting an electrical signal into an optical signal.

10. The eWLP package of claim 9 , wherein the EO converter chip is a light-emitting diode (LED) chip.

11. The eWLP package of claim 10 , wherein the third chip is an LED driver chip.

12. The eWLP package of claim 9 , wherein the EO converter chip is a laser diode chip.

13. The eWLP package of claim 12 , wherein the third chip is a laser diode driver chip.

14. The eWLP package of claim 9 , wherein the third chip is an optical-to-electrical (OE) converter chip that converts an optical signal received by the OE converter chip into an electrical signal.

15. The eWLP package of claim 14 , wherein the OE converter chip is a photodiode chip.

16. The eWLP package of claim 14 , wherein the second chip is a receiver chip for processing the electrical signal.

17. An embedded Wafer-Level Packaging (eWLP) package comprising:
at least first, second and third chips encapsulated inside of a molded material, the molded material having a front side and a back side, the front side of the molded material being co-planar with respective front sides of the first, second and third chips, a back side of the molded material being parallel to the front side of the molded material, the first, second and third chips having respective first electrical contacts disposed on respective front sides of the first, second and third chips and exposed thru the front side of the molded material, the first and third chips each having at least one second electrical contact disposed on a back side of the first and third chips; and
a metal layer disposed on the back side of the molded material, the second electrical contacts disposed on the back sides of the first and third chips being electrically coupled to the metal layer, the back side of the second chip being in contact with the metal layer, and wherein the second chip comprises a bulk material having a predetermined electrical conductivity that is sufficiently high for conducting electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip, and wherein a purpose of the second chip is to conduct electrical current from the first electrical contact disposed on the front side of the second chip to the back side of the second chip such that an electrical connection is made via the second chip and the metal layer to said at least one second electrical contact disposed on the back side of the first chip.

18. The eWLP package of claim 17 , wherein the first chip is an optical-to-electrical (OE) converter chip for converting an optical signal into an electrical signal, and wherein the third chip is a receiver chip for processing the electrical signal.

19. The eWLP package of claim 17 , wherein the first chip is an electrical-to-optical (EO) converter chip for converting an electrical signal into an optical signal.

20. The eWLP package of claim 19 , wherein the third chip is an optical-to-electrical (OE) converter chip that converts an optical signal received by the OE converter chip into an electrical signal.

21. An embedded Wafer-Level Packaging (eWLP) assembly comprising:
a circuit board (CB) having a plurality of electrical contacts disposed on a first surface thereof;
an eWLP package comprising:
at least first and second chips encapsulated inside of a molded material, the molded material having a front side and a back side, the front side of the molded material being co-planar with respective front sides of the first and second chips, a back side of the molded material being parallel to the front side of the molded material, the first and second chips having respective first electrical contacts disposed on respective front sides of the first and second chips and exposed thru the front side of the

Assignees

• Avago Technologies General Ip

Inventors

• Krabe Detlef Bernd
• Wittl Josef

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title